公开(公告)号：US5581705A

公开(公告)日：1996-12-03

申请号：US166443

申请日：1993-12-13

Applicant: Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

Inventor： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

IPC: G06F15/17 ,  G06F15/173 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16

CPC classification number: G06F15/17381

Abstract: A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

Abstract translation: 描述了消息传送设施，其能够在全局可寻址的分布式存储器多处理器中将数据分组从一个处理元件传递到另一处理元件，而不在目标处理元件的存储器中具有明确的目的地地址。 通过定义一个允许一个处理器将包含操作码，地址和参数的消息发送到另一个处理器的操作码约定，消息传递设施可用于完成远程操作。 目的处理器在到达中断之后收到消息后，可以解码操作码，并使用参数地址和数据执行指示的动作。 消息传递设备提供了构建处理器间通信协议的原语。 操作系统通信和消息传递编程模型可以使用消息传递设备来实现。

公开(公告)号：US5434995A

公开(公告)日：1995-07-18

申请号：US165265

申请日：1993-12-10

Applicant: Steven M. Oberlin ,  Eric C. Fromm

Inventor： Steven M. Oberlin ,  Eric C. Fromm

IPC: F02B75/02 ,  G06F9/46 ,  G06F15/16 ,  G06F15/80

CPC classification number: G06F9/52 ,  G06F9/522 ,  F02B2075/027

Abstract: A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size and shape. The barrier mask and interrupt register and the bypass points are used in concert to accomplish flexible and scalable partitions corresponding to user-desired sizes and shapes with a latency several orders of magnitude faster than existing software implementations.

Abstract translation: 屏障机制提供了在大规模并行处理系统中同步全部或一些处理元件（PE）的低等待时间方法。 屏障机制由几个物理屏障同步电路支持，每个物理屏障同步电路接收处理系统中每个PE的输入。 每个PE具有两个相关联的屏障同步寄存器，其中每个位用作多个逻辑屏障同步电路之一的输入。 该硬件支持传统的屏障功能和另一种尤里卡功能。 每个屏障同步寄存器中的每个位可以被编程为执行屏障或尤里卡功能，并且寄存器和每个屏障同步电路的所有位独立地起作用。 PE之间的分区是通过屏蔽掩码和中断寄存器实现的，这使得屏障同步寄存器中的某些位能够定义为一组PE。 通过在物理屏障同步电路中提供旁路点以将物理屏障同步电路细分为具有不同大小和形状的几种类型的PE屏障隔板来实现进一步划分。 屏蔽掩码和中断寄存器和旁路点一起用于完成与用户期望的大小和形状相对应的灵活和可扩展的分区，其延迟比现有软件实现快几个数量级。

公开(公告)号：US5420583A

公开(公告)日：1995-05-30

申请号：US250375

申请日：1994-05-27

Applicant: Kevin M. Knecht ,  Eric C. Fromm

Inventor： Kevin M. Knecht ,  Eric C. Fromm

IPC: H04L25/49 ,  H03M7/00

CPC classification number: H04L25/4906

Abstract: A digital optical serial communication system and encoding method comprises a transmitter responsive to an input of parallel information for parsing the information into 4-bit groups. The 4-bit groups are encoded into 5-bit codes having a 40/60 duty cycle and wherein no more than two consecutive bits are logical 1's or 0's on either end of the 5-bit code. The 5-bit codes are serially transmitted by an optical transmission medium for providing a conduit from the transmitter to a receiver. The receiver receives and decodes the serial information to 4-bit groups. The 4-bit groups are concatenated to form a parallel packet of information suitable for data processing. The encoding/decoding scheme has the advantages of (1) a worst case duty factor of 40/60%; (2) a maximum run of bits without transition equal to five; (3) an easily recaptured framing of packets due to a unique sync symbol; and (4) simple encoding and decoding of packets using combinational logic rather than lookup tables. In addition, data can be continuously sent via a communications protocol.

Abstract translation: 数字光串行通信系统和编码方法包括响应于并行信息的输入的发送器，用于将信息解析成4位组。 4位组被编码为具有40/60占空比的5位代码，并且其中不超过两个连续位是5位代码的任一端的逻辑1或0。 5位代码通过光传输介质串行传输，用于提供从发射机到接收机的导管。 接收器将串行信息接收并解码为4位组。 4位组被级联以形成适合于数据处理的并行信息包。 编码/解码方案具有以下优点：（1）最差情况占空比为40/60％; （2）无过渡等于5的最大位数; （3）由于唯一的同步符号而容易地重新分组分组; 和（4）使用组合逻辑而不是查找表对数据包进行简单的编码和解码。 此外，可以通过通信协议连续发送数据。

公开(公告)号：US08239566B2

公开(公告)日：2012-08-07

申请号：US12039048

申请日：2008-02-28

Applicant: Eric C. Fromm ,  Gregory M. Thorson

Inventor： Eric C. Fromm ,  Gregory M. Thorson

IPC: G06F15/16 ,  G06F15/167

CPC classification number: G06F9/5016 ,  G06F2209/5021

Abstract: Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.

Abstract translation: 描述在共享存储器多处理器计算机网络中处理事务请求。 在请求代理处的服务代理处接收到交易请求。 交易请求包括与请求代理产生的事务紧急性相关联的请求优先级。 服务代理根据请求优先级为交易请求提供分配的优先级，然后将分配的优先级与服务代理处的现有服务级别进行比较，以确定是否完成或拒绝交易请求。 产生从服务代理到请求代理的回复消息，以指示交易请求是否已完成或拒绝，并为拒绝的交易请求提供回复公平状态数据。

公开(公告)号：US06779072B1

公开(公告)日：2004-08-17

申请号：US09619722

申请日：2000-07-20

Applicant: Mark F. Sauder ,  Michael L. Anderson ,  Eric C. Fromm

Inventor： Mark F. Sauder ,  Michael L. Anderson ,  Eric C. Fromm

IPC: G06F1200

CPC classification number: G06F12/06 ,  G06F2212/206

Abstract: A method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit. Some embodiments provide a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request into the first integrated circuit, serially transmitting, through each of the plurality of logic subset modules, a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, and within the first logic subset module, accessing the memory-mapped register associated with the first logic subset module. Another aspect of the present invention provides an MMR circuit for accessing memory-mapped registers that are distributed across a first integrated circuit chip, the first integrated circuit chip including a plurality of logic subset modules.

Abstract translation: 一种用于访问分布在大型集成电路上的存储器映射寄存器的方法和装置。 一些实施例提供了一种用于访问分布在第一集成电路上的存储器映射寄存器的方法，第一集成电路包括多个逻辑子集模块，其中多个逻辑子集模块中的每一个包括一个或多个存储器映射寄存器。 该方法包括：将存储器映射的寄存器访问请求接收到第一集成电路中，基于存储器映射的寄存器访问请求，通过多个逻辑子集模块中的每一个串行地发送第一多个数据包，其中第一个多个 的数据分组包括与逻辑子集模块中的第一个相关联的存储器映射寄存器的地址规范，并且在第一逻辑子集模块内，访问与第一逻辑子集模块相关联的存储器映射寄存器。 本发明的另一方面提供一种用于访问分布在第一集成电路芯片上的存储器映射寄存器的MMR电路，该第一集成电路芯片包括多个逻辑子集模块。

公开(公告)号：US5784706A

公开(公告)日：1998-07-21

申请号：US165814

申请日：1993-12-13

Applicant: Steven M. Oberlin ,  Eric C. Fromm ,  Randal S. Passint

Inventor： Steven M. Oberlin ,  Eric C. Fromm ,  Randal S. Passint

IPC: G06F15/17 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/06

CPC classification number: G06F12/1072 ,  G06F12/0284

Abstract: Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

Abstract translation: 用于分布式存储器大规模并行处理（MPP）系统的地址转换装置包括用于在程序控制下定义用于处理元件（PE）和相对于PE的分区的存储器的虚拟地址的装置，用于在三维空间中定义PE和存储器的逻辑地址的装置， MPP中PE的三维互联网络以及PE和内存的物理地址对应于计算机机柜内PE模块的标识和位置。 由于物理PE被映射到逻辑MPP或从逻辑MPP映射，因为需要备用，所以更新逻辑地址。 由虚拟地址模式下的分区内的PE生成的地址引用转换为逻辑地址和物理地址，用于在网络上进行路由。

公开(公告)号：US5765181A

公开(公告)日：1998-06-09

申请号：US165118

申请日：1993-12-10

Applicant: Steven M. Oberlin ,  Janet M. Eberhart ,  Gary W. Elsesser ,  Eric C. Fromm ,  Thomas A. MacDonald ,  Douglas M. Pase ,  Randal S. Passint

Inventor： Steven M. Oberlin ,  Janet M. Eberhart ,  Gary W. Elsesser ,  Eric C. Fromm ,  Thomas A. MacDonald ,  Douglas M. Pase ,  Randal S. Passint

IPC: G06F12/06 ,  G06F15/173 ,  G06F12/00

CPC classification number: G06F15/17381 ,  G06F12/0692

Abstract: A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in an array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a distribution specification associated with the array. In addition, a local memory address associated with the array element is computed as a function of the linearized index and the distribution specification.

Abstract translation: 一种用于提取PE数字和从数组索引偏移的系统和地址方法。 根据本发明的一个方面，处理单元编号被分配给每个处理单元，将本地存储器地址分配给每个存储器单元，并且将线性化索引分配给阵列中的每个阵列元素。 作为与数组元素相关联的线性化索引和与阵列相关联的分布规范的函数来计算其中存储特定数组元素的处理元件的处理元件号。 另外，与数组元素相关联的本地存储器地址被计算为线性化索引和分布规范的函数。

公开(公告)号：US5390041A

公开(公告)日：1995-02-14

申请号：US788496

申请日：1991-11-06

Applicant: Kevin M. Knecht ,  Eric C. Fromm

Inventor： Kevin M. Knecht ,  Eric C. Fromm

IPC: H04L25/49 ,  H04B10/12

CPC classification number: H04L25/4906

Abstract: A digital optical serial communication system and encoding method comprises a transmitter responsive to an input of parallel information for parsing the information into 4-bit groups. The 4-bit groups are encoded into 5-bit codes having a 40/60 duty cycle and wherein no more than two consecutive bits are logical 1's or 0's on either end of the 5-bit code. The 5-bit codes are serially transmitted by an optical transmission medium for providing a conduit from the transmitter to a receiver. The receiver receives and decodes the serial information to 4-bit groups. The 4-bit groups are concatenated to form a parallel packet of information suitable for data processing. The encoding/decoding scheme has the advantages of (1) a worst case duty factor of 40/60%; (2) a maximum run of bits without transition equal to five; (3) an easily recaptured framing of packets due to a unique sync symbol; and (4) simple encoding and decoding of packets using combinational logic rather than lookup tables. In addition, data can be continuously sent via a communications protocol.

公开(公告)号：US5321697A

公开(公告)日：1994-06-14

申请号：US890026

申请日：1992-05-28

Applicant: Eric C. Fromm ,  Michael L. Anderson ,  Lonnie R. Heidtke

Inventor： Eric C. Fromm ,  Michael L. Anderson ,  Lonnie R. Heidtke

IPC: G06F12/16 ,  G06F12/00 ,  G11C11/406 ,  G11C29/00 ,  G06F11/00

CPC classification number: G11C29/765 ,  G11C11/406 ,  G11C29/88

Abstract: An improved solid state storage device (SSD) with memory organized into a plurality of groups, each group including a plurality of ranks, and each rank having at least two banks sharing a bidirectional data bus. A matrix reorder circuit is used to distribute data across individual memory components in a way that prevents multibit uncorrectable or undetectable errors due to the failure of a single memory component. The matrix reorder circuit is used for both reading and writing data, and operates on a stream of pipelined data of arbitrary length.According to another aspect of this invention, a flaw map and additional hot spare memory are used to electrically replace failing memory components in theAccording to another aspect of this invention, memory in a bank is accessed during one half of a reference cycle and refreshed during the second half of the reference cycle, each bank being 180 degrees out of phase with the other so that a read or write is performed on one bank while a memory refresh is performed on the other bank.

Abstract translation: 一种具有被组织成多个组的存储器的改进的固态存储设备（SSD），每个组包括多个等级，并且每个等级具有共享双向数据总线的至少两个存储体。 矩阵重排序电路用于以单个存储器组件的故障防止多位不可校正或不可检测的错误的方式在各个存储器组件之间分布数据。 矩阵重排电路用于读取和写入数据，并且对任意长度的流水线数据流进行操作。 根据本发明的另一方面，使用缺陷图和额外的热备用存储器来电代替故障存储器组件。根据本发明的另一方面，在参考周期的一半期间访问存储体中的存储器并在 在参考周期的后半段，每个存储体与另一个存储体相差180度，使得在对另一个存储体执行存储器刷新的同时对一个存储体执行读取或写入。

公开(公告)号：US4951246A

公开(公告)日：1990-08-21

申请号：US391229

申请日：1989-08-08

Applicant: Eric C. Fromm ,  Lonnie R. Heidtke

Inventor： Eric C. Fromm ,  Lonnie R. Heidtke

IPC: G06F12/06 ,  G06F12/02 ,  G11C7/10 ,  G11C11/401

CPC classification number: G11C7/1033 ,  G11C7/1039

Abstract: A nibble-mode DRAM solid state storage device is organized into a plurality of sections each including a plurality of groups, each including a plurality of ranks of DRAM memory chips. A pipeline data path is provided into and out of each group and nibble-mode access is facilitated by simultaneous pipelining of data into and out of the memory while memory reference operations are accomplished.

Abstract translation: 半字模式DRAM固态存储设备被组织成多个部分，每个部分包括多个组，每个组包括多个等级的DRAM存储器芯片。 每个组中提供流水线数据路径，并且通过在完成存储器参考操作的同时将数据流入和移出存储器来促进半字节模式访问。