公开(公告)号：US5835925A

公开(公告)日：1998-11-10

申请号：US615671

申请日：1996-03-13

申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/355 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3861

摘要： A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

摘要翻译： 一种访问具有处理器和与处理器分离的多个存储器位置的系统内的存储器位置的系统和方法。 该系统包括通过数据总线连接到处理器的多个外部寄存器，通过数据总线连接到处理器的地址转换装置和地址总线，用于基于写入数据总线的索引来计算 连接到多个外部寄存器的传送装置，用于在寻址的存储器位置和外部寄存器之一之间传送数据。

公开(公告)号：US6029212A

公开(公告)日：2000-02-22

申请号：US6449

申请日：1998-01-13

申请人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

发明人： Richard E. Kessler ,  Steven M. Oberlin ,  Steven L. Scott ,  Eric C. Fromm

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/355 ,  G06F12/02 ,  G06F13/14 ,  G06F15/163

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/3861

摘要： A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

摘要翻译： 一种访问具有处理器和与处理器分离的多个存储器位置的系统内的存储器位置的系统和方法。 该系统包括通过数据总线连接到处理器的多个外部寄存器，通过数据总线连接到处理器的地址转换装置和地址总线，用于基于写入数据总线的索引来计算 连接到多个外部寄存器的传送装置，用于在寻址的存储器位置和外部寄存器之一之间传送数据。

公开(公告)号：US5581705A

公开(公告)日：1996-12-03

申请号：US166443

申请日：1993-12-13

申请人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

发明人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16

CPC分类号： G06F15/17381

摘要： A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

摘要翻译： 描述了消息传送设施，其能够在全局可寻址的分布式存储器多处理器中将数据分组从一个处理元件传递到另一处理元件，而不在目标处理元件的存储器中具有明确的目的地地址。 通过定义一个允许一个处理器将包含操作码，地址和参数的消息发送到另一个处理器的操作码约定，消息传递设施可用于完成远程操作。 目的处理器在到达中断之后收到消息后，可以解码操作码，并使用参数地址和数据执行指示的动作。 消息传递设备提供了构建处理器间通信协议的原语。 操作系统通信和消息传递编程模型可以使用消息传递设备来实现。

公开(公告)号：US5434995A

公开(公告)日：1995-07-18

申请号：US165265

申请日：1993-12-10

申请人： Steven M. Oberlin ,  Eric C. Fromm

发明人： Steven M. Oberlin ,  Eric C. Fromm

IPC分类号： F02B75/02 ,  G06F9/46 ,  G06F15/16 ,  G06F15/80

CPC分类号： G06F9/52 ,  G06F9/522 ,  F02B2075/027

摘要： A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size and shape. The barrier mask and interrupt register and the bypass points are used in concert to accomplish flexible and scalable partitions corresponding to user-desired sizes and shapes with a latency several orders of magnitude faster than existing software implementations.

摘要翻译： 屏障机制提供了在大规模并行处理系统中同步全部或一些处理元件（PE）的低等待时间方法。 屏障机制由几个物理屏障同步电路支持，每个物理屏障同步电路接收处理系统中每个PE的输入。 每个PE具有两个相关联的屏障同步寄存器，其中每个位用作多个逻辑屏障同步电路之一的输入。 该硬件支持传统的屏障功能和另一种尤里卡功能。 每个屏障同步寄存器中的每个位可以被编程为执行屏障或尤里卡功能，并且寄存器和每个屏障同步电路的所有位独立地起作用。 PE之间的分区是通过屏蔽掩码和中断寄存器实现的，这使得屏障同步寄存器中的某些位能够定义为一组PE。 通过在物理屏障同步电路中提供旁路点以将物理屏障同步电路细分为具有不同大小和形状的几种类型的PE屏障隔板来实现进一步划分。 屏蔽掩码和中断寄存器和旁路点一起用于完成与用户期望的大小和形状相对应的灵活和可扩展的分区，其延迟比现有软件实现快几个数量级。

公开(公告)号：US5784706A

公开(公告)日：1998-07-21

申请号：US165814

申请日：1993-12-13

申请人： Steven M. Oberlin ,  Eric C. Fromm ,  Randal S. Passint

发明人： Steven M. Oberlin ,  Eric C. Fromm ,  Randal S. Passint

IPC分类号： G06F15/17 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/06

CPC分类号： G06F12/1072 ,  G06F12/0284

摘要： Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

摘要翻译： 用于分布式存储器大规模并行处理（MPP）系统的地址转换装置包括用于在程序控制下定义用于处理元件（PE）和相对于PE的分区的存储器的虚拟地址的装置，用于在三维空间中定义PE和存储器的逻辑地址的装置， MPP中PE的三维互联网络以及PE和内存的物理地址对应于计算机机柜内PE模块的标识和位置。 由于物理PE被映射到逻辑MPP或从逻辑MPP映射，因为需要备用，所以更新逻辑地址。 由虚拟地址模式下的分区内的PE生成的地址引用转换为逻辑地址和物理地址，用于在网络上进行路由。

公开(公告)号：US5765181A

公开(公告)日：1998-06-09

申请号：US165118

申请日：1993-12-10

申请人： Steven M. Oberlin ,  Janet M. Eberhart ,  Gary W. Elsesser ,  Eric C. Fromm ,  Thomas A. MacDonald ,  Douglas M. Pase ,  Randal S. Passint

发明人： Steven M. Oberlin ,  Janet M. Eberhart ,  Gary W. Elsesser ,  Eric C. Fromm ,  Thomas A. MacDonald ,  Douglas M. Pase ,  Randal S. Passint

IPC分类号： G06F12/06 ,  G06F15/173 ,  G06F12/00

CPC分类号： G06F15/17381 ,  G06F12/0692

摘要： A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in an array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a distribution specification associated with the array. In addition, a local memory address associated with the array element is computed as a function of the linearized index and the distribution specification.

摘要翻译： 一种用于提取PE数字和从数组索引偏移的系统和地址方法。 根据本发明的一个方面，处理单元编号被分配给每个处理单元，将本地存储器地址分配给每个存储器单元，并且将线性化索引分配给阵列中的每个阵列元素。 作为与数组元素相关联的线性化索引和与阵列相关联的分布规范的函数来计算其中存储特定数组元素的处理元件的处理元件号。 另外，与数组元素相关联的本地存储器地址被计算为线性化索引和分布规范的函数。

公开(公告)号：US06925547B2

公开(公告)日：2005-08-02

申请号：US10017488

申请日：2001-12-14

申请人： Steven L. Scott ,  Chris Dickson ,  Eric C. Fromm ,  Michael L. Anderson

发明人： Steven L. Scott ,  Chris Dickson ,  Eric C. Fromm ,  Michael L. Anderson

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/1072 ,  G06F12/1027

摘要： A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node, accessing a local connection table at the local node using the connection descriptor to produce a system node identifier for a remote node and a remote address space number, communicating the virtual address and remote address space number to the remote node, and translating the virtual address to a physical address at the remote node (qualified by the remote address space number). A user process running at the local node provides the connection descriptor and virtual address. The translation is performed by matching the virtual address and remote address space number with an entry of a translation-lookaside buffer (TLB) at the remote node. Performing the translation at the remote node reduces the amount of translation information needed at the local node for remote memory accesses. The method supports communication within a scalable multiprocessor, and across the machine boundaries in a cluster.

摘要翻译： 在多处理器系统中执行远程地址转换的方法包括确定本地节点处的连接描述符和虚拟地址，使用连接描述符访问本地节点处的本地连接表，以产生远程节点的系统节点标识符，以及 远程地址空间号码，将虚拟地址和远程地址空间号码传送到远程节点，并将虚拟地址转换为远程节点的物理地址（由远程地址空间号限定）。 在本地节点运行的用户进程提供连接描述符和虚拟地址。 通过将虚拟地址和远程地址空间编号与远程节点上的翻译后备缓冲区（TLB）的条目进行匹配来执行翻译。 在远程节点执行翻译可减少本地节点为远程存储器访问所需的翻译信息量。 该方法支持可扩展多处理器内的通信，并支持集群中的机器边界。

公开(公告)号：US06604185B1

公开(公告)日：2003-08-05

申请号：US09619851

申请日：2000-07-20

申请人： Eric C. Fromm

发明人： Eric C. Fromm

IPC分类号： G06F1212

CPC分类号： G06F12/1072 ,  G06F12/1027 ,  G06F2212/682

摘要： A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a virtual address specified in the PTC instruction from the processor's translation lookaside buffer. By purging the virtual address, the memory is deallocated.

摘要翻译： 一种用于在多处理器共享存储器系统中释放存储器的方法和装置。 在一个方面，系统中的节点具有包含排序逻辑的节点控制器。 排序逻辑通过网络接收命令。 排序逻辑将接收到的命令转换为清除转换缓存（PTC）指令，并将总线上的PTC指令发送到处理器。 该处理器包含总线控制逻辑，接收PTC指令，并从处理器的转换后备缓冲器清除PTC指令中指定的虚拟地址。 通过清除虚拟地址，释放内存。

公开(公告)号：US6119198A

公开(公告)日：2000-09-12

申请号：US889251

申请日：1997-07-08

申请人： Eric C. Fromm

发明人： Eric C. Fromm

IPC分类号： G06F7/76 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F12/04 ,  G06F5/01

CPC分类号： G06F15/8007 ,  G06F12/0692 ,  G06F15/17381 ,  G06F7/762

摘要： A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in a multidimensional array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a mask word determined from the distribution specification associated with the array. The mask word is generated from the distribution specification and applied to a linearized index associated with a particular array element to obtain processing element number bits and local offset bits. The processing element number bits and local offset bits are then accumulated to create the processing element number and local offset for the memory location associated with the array element.

摘要翻译： 通过递归离心提取PE数和从数组索引偏移的方法。 根据本发明的一个方面，处理单元编号被分配给每个处理单元，将局部存储器地址分配给每个存储器单元，并且线性化索引被分配给多维阵列中的每个阵列元素。 作为与阵列元素相关联的线性化索引和从与阵列相关联的分布规范确定的掩码字的函数来计算其中存储特定数组元素的处理元件的处理元件号。 掩模字从分布规范生成并应用于与特定数组元素相关联的线性化索引，以获得处理元素数位和局部偏移位。 然后累积处理元件数位和局部偏移位以产生与数组元素相关联的存储器位置的处理元件号和本地偏移。

公开(公告)号：US20090222821A1

公开(公告)日：2009-09-03

申请号：US12039048

申请日：2008-02-28

申请人： Eric C. Fromm ,  Gregory M. Thorson

发明人： Eric C. Fromm ,  Gregory M. Thorson

IPC分类号： G06F9/50

CPC分类号： G06F9/5016 ,  G06F2209/5021

摘要： Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.

摘要翻译： 描述在共享存储器多处理器计算机网络中处理事务请求。 在请求代理处的服务代理处接收到交易请求。 交易请求包括与请求代理产生的事务紧急性相关联的请求优先级。 服务代理根据请求优先级为交易请求提供分配的优先级，然后将分配的优先级与服务代理处的现有服务级别进行比较，以确定是否完成或拒绝交易请求。 产生从服务代理到请求代理的回复消息，以指示交易请求是否已完成或拒绝，并为拒绝的交易请求提供回复公平状态数据。