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    Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system
    1.
    发明授权
    Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system 失效
    具有硬件尾部指针和软件的消息传递设施实现了分布式存储器大规模并行处理系统的头指针消息队列

    公开(公告)号：US5581705A

    公开(公告)日：1996-12-03

    申请号：US166443

    申请日：1993-12-13

    申请人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

    发明人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

    IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16

    CPC分类号： G06F15/17381

    摘要： A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

    摘要翻译： 描述了消息传送设施，其能够在全局可寻址的分布式存储器多处理器中将数据分组从一个处理元件传递到另一处理元件，而不在目标处理元件的存储器中具有明确的目的地地址。 通过定义一个允许一个处理器将包含操作码，地址和参数的消息发送到另一个处理器的操作码约定，消息传递设施可用于完成远程操作。 目的处理器在到达中断之后收到消息后，可以解码操作码，并使用参数地址和数据执行指示的动作。 消息传递设备提供了构建处理器间通信协议的原语。 操作系统通信和消息传递编程模型可以使用消息传递设备来实现。

    Virtual to logical to physical address translation for distributed memory massively parallel processing systems
    2.
    发明授权
    Virtual to logical to physical address translation for distributed memory massively parallel processing systems 失效
    虚拟到逻辑到分布式存储器大规模并行处理系统的物理地址转换

    公开(公告)号：US5784706A

    公开(公告)日：1998-07-21

    申请号：US165814

    申请日：1993-12-13

    申请人： Steven M. Oberlin ,  Eric C. Fromm ,  Randal S. Passint

    发明人： Steven M. Oberlin ,  Eric C. Fromm ,  Randal S. Passint

    IPC分类号： G06F15/17 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/06

    CPC分类号： G06F12/1072 ,  G06F12/0284

    摘要： Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

    摘要翻译： 用于分布式存储器大规模并行处理（MPP）系统的地址转换装置包括用于在程序控制下定义用于处理元件（PE）和相对于PE的分区的存储器的虚拟地址的装置，用于在三维空间中定义PE和存储器的逻辑地址的装置， MPP中PE的三维互联网络以及PE和内存的物理地址对应于计算机机柜内PE模块的标识和位置。 由于物理PE被映射到逻辑MPP或从逻辑MPP映射，因为需要备用，所以更新逻辑地址。 由虚拟地址模式下的分区内的PE生成的地址引用转换为逻辑地址和物理地址，用于在网络上进行路由。

    Barrier synchronization for distributed memory massively parallel processing systems
    9.
    发明授权
    Barrier synchronization for distributed memory massively parallel processing systems 失效
    分布式存储器大规模并行处理系统的屏障同步

    公开(公告)号：US5434995A

    公开(公告)日：1995-07-18

    申请号：US165265

    申请日：1993-12-10

    申请人： Steven M. Oberlin ,  Eric C. Fromm

    发明人： Steven M. Oberlin ,  Eric C. Fromm

    IPC分类号： F02B75/02 ,  G06F9/46 ,  G06F15/16 ,  G06F15/80

    CPC分类号： G06F9/52 ,  G06F9/522 ,  F02B2075/027

    摘要： A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size and shape. The barrier mask and interrupt register and the bypass points are used in concert to accomplish flexible and scalable partitions corresponding to user-desired sizes and shapes with a latency several orders of magnitude faster than existing software implementations.

    摘要翻译： 屏障机制提供了在大规模并行处理系统中同步全部或一些处理元件（PE）的低等待时间方法。 屏障机制由几个物理屏障同步电路支持，每个物理屏障同步电路接收处理系统中每个PE的输入。 每个PE具有两个相关联的屏障同步寄存器，其中每个位用作多个逻辑屏障同步电路之一的输入。 该硬件支持传统的屏障功能和另一种尤里卡功能。 每个屏障同步寄存器中的每个位可以被编程为执行屏障或尤里卡功能，并且寄存器和每个屏障同步电路的所有位独立地起作用。 PE之间的分区是通过屏蔽掩码和中断寄存器实现的，这使得屏障同步寄存器中的某些位能够定义为一组PE。 通过在物理屏障同步电路中提供旁路点以将物理屏障同步电路细分为具有不同大小和形状的几种类型的PE屏障隔板来实现进一步划分。 屏蔽掩码和中断寄存器和旁路点一起用于完成与用户期望的大小和形状相对应的灵活和可扩展的分区，其延迟比现有软件实现快几个数量级。

    Application-based specialization for computing nodes within a distributed processing system
    10.
    发明授权
    Application-based specialization for computing nodes within a distributed processing system 有权
    基于应用程序的分布式处理系统中计算节点的专业化

    公开(公告)号：US08656355B2

    公开(公告)日：2014-02-18

    申请号：US13437752

    申请日：2012-04-02

    申请人： Steven M. Oberlin ,  David W. McAllister

    发明人： Steven M. Oberlin ,  David W. McAllister

    IPC分类号： G06F9/44 ,  G06F9/445 ,  G06F15/00 ,  G06F15/76 ,  G06F15/16 ,  G06F15/167

    CPC分类号： G06F9/5055 ,  G06F9/5072

    摘要： A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.

    摘要翻译： 描述了采用“基于应用”的专业化的分布式处理系统。 特别地，分布式处理系统被构造为计算节点的集合，其中每个计算节点在整个分布式处理系统的操作中执行特定的处理角色。 每个计算节点包括诸如Linux操作系统的操作系统，并且包括插件软件模块，以提供采用基于角色的计算技术的分布式存储器操作系统。 管理节点维护定义多个应用角色的数据库。 每个角色与软件应用程序相关联，并指定执行软件应用程序所需的一组软件组件。 管理节点根据与每个应用节点相关联的应用角色将软件组件部署到应用节点。