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11.发明授权Parallel data communications mechanism having reduced power continuously calibrated lines 有权并行数据通信机制具有降低功率的连续校准线路公开(公告)号：US08898504B2
公开(公告)日：2014-11-25
申请号：US13325478
申请日：2011-12-14
IPC分类号： G06F11/00
CPC分类号： H04L1/22
摘要： A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N
摘要翻译： 通信链路包括多个连续校准的并行线路，其中一个或多个线路被至少部分断电，同时连续校准以减少功率消耗。 在一个方面，至少N + 1行（其中N是逻辑总线宽度）被周期性地重新校准，并且至少一个冗余线路在校准之间断电。 冗余线路可以是可用作替代的真实备用，也可以是携带功能数据的额外线路，而其他线路依次校准。 另一方面，逻辑总线宽度是可变的，但不超过NMAX。 当N
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12.发明申请公开(公告)号：US20130159761A1
公开(公告)日：2013-06-20
申请号：US13325478
申请日：2011-12-14
CPC分类号： H04L1/22
摘要： A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed NMAX. When N
摘要翻译： 通信链路包括多个连续校准的并行线路，其中一个或多个线路被至少部分断电，同时连续校准以减少功率消耗。 在一个方面，至少N + 1行（其中N是逻辑总线宽度）被周期性地重新校准，并且至少一个冗余线路在校准之间断电。 冗余线路可以是可用作替代的真实备用，也可以是携带功能数据的额外线路，而其他线路依次被校准。 另一方面，逻辑总线宽度是可变的，但不超过NMAX。 当N
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公开(公告)号：US08018837B2
公开(公告)日：2011-09-13
申请号：US12635121
申请日：2009-12-10
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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公开(公告)号：US20100005345A1
公开(公告)日：2010-01-07
申请号：US12165799
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于存储器系统中的位阴影的通信接口设备，系统，方法和设计结构。 通信接口设备包括用于选择驱动器位位置作为阴影驱动器值的阴影选择逻辑，以及线驱动器，以在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 通信接口设备还包括阴影比较逻辑，以将所选择的接收值与来自总线的阴影接收值进行比较，并且识别响应于比较不匹配的错误比较，以及阴影计数器来计数相对于总线的误比率 错误率在一段时间内。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
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公开(公告)号：US07461287B2
公开(公告)日：2008-12-02
申请号：US11055866
申请日：2005-02-11
摘要： A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.
摘要翻译： 用于在弹性界面上在两个芯片之间发送的数据位的偏斜和对准的机制。 在弹性接口的接收端，时钟/数据组内的每个数据位的眼睛被延迟小于一点时间，以使眼睛与接收到的时钟信号的最近的时钟沿对齐。 除了将各个数据位的眼睛与最近的时钟边沿对齐之外，还使用IAP模式来确定从每个数据位排列各个数据节拍所需的进一步延迟量。 如果数据位的数据跳转不对齐，除了最慢的数据跳转之外，除了所有位的数据跳转之外，都会被延迟。 使用采样锁存器实现额外的延迟，导致延迟信号抖动较小。 由于具有较少的抖动，所接收的，去偏斜的和对准的时钟/数据组可以以增加的频率转发到接收芯片的操作部分。
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公开(公告)号：US08082475B2
公开(公告)日：2011-12-20
申请号：US12165848
申请日：2008-07-01
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。 此外，阴影比较逻辑用于将选定的接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线错误率的速率 经过一段时间。 响应于在总线错误率的预定义阈值内的错误比较的速率来识别有缺陷的链路段。
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公开(公告)号：US20100005202A1
公开(公告)日：2010-01-07
申请号：US12165809
申请日：2008-07-01
IPC分类号： G06F3/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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公开(公告)号：US07443940B2
公开(公告)日：2008-10-28
申请号：US11055841
申请日：2005-02-11
IPC分类号： H04L25/00
CPC分类号： G11C19/287 , G06F5/10 , G06F2205/104
摘要： Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if the data was sent on falling clock edges, or on the nearest clock edge if minimum latency is desired. Alternatively, data bits can be delayed by one or more bit times before loading into FIFO latches to reduce the elastic interface system's sensitivity to drift. The present invention permits a user to trade off factors related to for latency, drift, and skew by choosing among different alignment modes in an elastic interface system.
摘要翻译： 公开了用于在弹性界面系统中对准接收数据位的方法和装置。 根据选择的几种对准模式中的哪一种，如果数据在上升时钟沿发送，则数据位可以在上升时钟沿加载到FIFO锁存器中，如果数据在下降时钟沿发送，则在下降时钟沿 如果需要最小延迟，则为最近的时钟沿。 或者，数据位可以在加载到FIFO锁存器之前延迟一个或多个位时间，以减少弹性接口系统对漂移的敏感度。 本发明允许用户通过在弹性接口系统中的不同对准模式之间进行选择来折衷与延迟，漂移和偏斜相关的因素。
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公开(公告)号：US20100005335A1
公开(公告)日：2010-01-07
申请号：US12165858
申请日：2008-07-01
CPC分类号： G06F11/2007
摘要： A processing device, system, method, and design structure for providing a microprocessor interface with dynamic segment sparing and repair. The processing device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译： 一种处理设备，系统，方法和设计结构，用于提供具有动态段保存和修复的微处理器接口。 处理装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。
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