公开(公告)号：US20150074787A1

公开(公告)日：2015-03-12

申请号：US14480330

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: H04L29/06

CPC classification number: G06F13/385

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

Abstract translation: 为具有分层令牌系统的异步处理器提供实施例。 异步处理器包括一组主处理单元，其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。 异步处理器还包括一组辅助单元，其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。 主令牌系统的令牌集合包括在主处理单元组中消耗的令牌，并被指定用于触发该次要单元组中的辅助令牌系统。

公开(公告)号：US20150074446A1

公开(公告)日：2015-03-12

申请号：US14480531

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Wen Tong ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Huang Tao

IPC: G06F1/08

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

Abstract translation: 无时钟异步处理电路或系统利用自定时发生器来调整电路/系统中处理周期所需/允许的处理延迟（等待时间）。 自定时发生器的定时可根据各种参数动态调整。 这些参数可以包括处理指令，操作码信息，由电路/系统执行的处理类型或整体期望的处理性能。 还可以调整延迟以改变处理性能，包括功耗，速度等。

公开(公告)号：US20150074443A1

公开(公告)日：2015-03-12

申请号：US14480491

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Tao Huang ,  Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Wen Tong

IPC: G06F1/08

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

Abstract translation: 无时钟异步处理电路或系统被配置为以多种模式操作。 在初始化模式（例如，复位，初始化，启动）中，与异步电路相关联的自定时发生器被配置为在接收到触发之后的第一时间段内产生有效完成信号（锁存输出处理的数据） 信号。 在正常模式下，自定时发生器被配置为在接收到触发信号之后的第二时间段内产生有效完成信号。 在一个实施例中，在初始化模式期间，异步电路比正常模式下的锁存输出慢。

公开(公告)号：US20150074379A1

公开(公告)日：2015-03-12

申请号：US14480035

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3871 ,  G06F9/3836 ,  G06F9/3885 ,  G06F13/4204 ,  G06F13/4282

Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.

Abstract translation: 为具有基于令牌的非常长的指令字架构的异步处理器提供实施例。 异步处理器包括被配置为高速缓存多个指令的存储器，被配置为一次接收指令集合（被称为非常长的指令字）并且解码指令的反馈引擎，以及被配置为 转移计算信息和异步处理器的结果。 该装置还包括在反馈引擎和交叉开关总线之间的多组执行单元（XU）。 每组XU包括串联布置的多个XU并且被配置为处理从反馈引擎在每个集合处接收到的一组指令。