中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.013 seconds)

    System and Method for an Asynchronous Processor with Heterogeneous Processors
    3.
    发明申请
    System and Method for an Asynchronous Processor with Heterogeneous Processors 审中-公开
    具有异构处理器的异步处理器的系统和方法

    公开(公告)号：US20150074378A1

    公开(公告)日：2015-03-12

    申请号：US14480541

    申请日：2014-09-08

    Applicant: Futurewei Technologies, Inc.

    Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

    IPC: G06F9/30

    CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3871

    Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

    Abstract translation: 为具有异构处理器的异步处理器提供实施例。 在一个实施例中，用于异步处理器的装置包括被配置为缓存指令的存储器以及被配置为处理指令的第一指令的第一单元（XU）。 所述装置还包括第二XU，其具有比所述第一XU更少受限于所述异步处理器的资源的访问，并被配置为处理所述指令的第二指令。 第二条指令需要访问资源。 所述装置还包括被配置为对所述第一指令和所述第二指令进行解码并且向所述第一XU发出所述第一指令的反馈引擎，以及被配置为向所述第二XU发送所述第二指令的调度器。

    System and Method for an Asynchronous Processor with Pepelined Arithmetic and Logic Unit
    4.
    发明申请
    System and Method for an Asynchronous Processor with Pepelined Arithmetic and Logic Unit 审中-公开
    具有混合算术和逻辑单元的异步处理器的系统和方法

    公开(公告)号：US20150074377A1

    公开(公告)日：2015-03-12

    申请号：US14477536

    申请日：2014-09-04

    Applicant: Futurewei Technologies, Inc.

    Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

    IPC: G06F9/38

    CPC classification number: G06F9/3871 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/4494

    Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

    Abstract translation: 为具有流水线算术和逻辑单元的异步处理器提供实施例。 异步处理器包括用于存储指令的非暂存存储器和布置在用于传递令牌的环形架构中的多个指令执行单元（XU）。 XU中的每一个包括被配置为从非暂时存储器获取第一指令并执行第一指令的逻辑电路。 逻辑电路还被配置为从非瞬时存储器获取第二指令，并且执行第二指令，而不管XU中的一个是否存储用于写入第一指令的令牌。 逻辑电路还被配置为在获取第二指令之后将第一指令写入非暂时存储器。

    System and Method for an Asynchronous Processor with Assisted Token
    5.
    发明申请
    System and Method for an Asynchronous Processor with Assisted Token 有权
    具有辅助令牌的异步处理器的系统和方法

    公开(公告)号：US20150074376A1

    公开(公告)日：2015-03-12

    申请号：US14480562

    申请日：2014-09-08

    Applicant: Futurewei Technologies, Inc.

    Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

    IPC: G06F15/82 ,  G06F9/30

    CPC classification number: G06F15/825 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3871

    Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

    Abstract translation: 为使用主和辅助令牌的异步处理器提供实施例。 在一个实施例中，用于异步处理器的装置包括用于高速缓存多个指令的存储器，用于对来自存储器的指令进行解码的反馈引擎，以及耦合到反馈引擎并以令牌环结构排列的多个XU。 每个XU被配置为从反馈引擎接收指令的指令，并且接收与资源相关联的主令牌，并且还接收主令牌的辅助令牌。 在确定以异常顺序接收到辅助令牌和主令牌之后，XU被配置为检测与辅助令牌相关联的指令的操作状态，并且在根据操作状态确定所需动作时， 辅助令牌，执行所需的操作。

    Bi-directional ring-bus architecture for CORDIC-based matrix inversion
    6.
    发明授权
    Bi-directional ring-bus architecture for CORDIC-based matrix inversion 有权
    基于CORDIC的矩阵反演的双向环形总线架构

    公开(公告)号：US08824603B1

    公开(公告)日：2014-09-02

    申请号：US13782328

    申请日：2013-03-01

    Applicant: Futurewei Technologies, Inc.

    Inventor： Yiqun Ge ,  Qifan Zhang ,  Peter Man Kin Sinn

    IPC: H04L27/06

    CPC classification number: H04B7/0413 ,  G06F7/4818

    Abstract: A method and a system is provided for Coordinate Rotation Digital Computer (CORDIC) based matrix inversion of input digital signal streams from multiple antennas using an bi-directional ring-bus architecture. The bi-directional ring bus includes a first ring bus having signals flow in a clockwise direction, and a second ring bus having signals flow in a counter-clockwise direction. An I/O controller is coupled to the first and the second ring bus, respectively. A plurality of processing elements (PEs), where each of the plurality of PEs is coupled to the first and the second ring bus, respectively, wherein each of the plurality of PEs includes at least one CORDIC core for performing CORDIC iterations on the plurality of input digital stream signals to produce inversed matrix signals.

    Abstract translation: 提供了一种用于使用双向环形总线架构从多个天线输入数字信号流的坐标旋转数字计算机（CORDIC）矩阵求逆的方法和系统。 双向环形总线包括具有沿顺时针方向流动的信号的第一环形总线和具有逆时针方向的信号的第二环形总线。 I / O控制器分别耦合到第一和第二环形总线。 多个处理元件（PE），其中所述多个PE中的每一个分别耦合到所述第一和第二环形总线，其中所述多个PE中的每一个包括用于在所述多个PE中执行CORDIC迭代的至少一个CORDIC内核 输入数字流信号以产生反相矩阵信号。

    Systems and methods for a long-term evolution network
    7.
    发明授权
    Systems and methods for a long-term evolution network 有权
    长期演进网络的系统和方法

    公开(公告)号：US09231667B2

    公开(公告)日：2016-01-05

    申请号：US13774495

    申请日：2013-02-22

    Applicant: Futurewei Technologies, Inc.

    Inventor： Yiqun Ge

    IPC: H04B15/00 ,  H04B7/02 ,  H04W56/00 ,  H04B7/06

    CPC classification number: H04B7/024 ,  H04B7/0626 ,  H04J11/004 ,  H04J11/0053 ,  H04W56/0015

    Abstract: A system and method for a LTE network device is provided. The system includes a first signal processing center configured to obtain a plurality of metrics from an LTE network device. The first signal processing center includes a plurality of processors configured to calculate interference based on the plurality of metrics. The signal processing system further includes a second signal processing center configured to receive the calculated interference from the first signal processing center.

    Abstract translation: 提供了一种用于LTE网络设备的系统和方法。 该系统包括被配置为从LTE网络设备获得多个度量的第一信号处理中心。 第一信号处理中心包括被配置为基于多个度量来计算干扰的多个处理器。 信号处理系统还包括被配置为从第一信号处理中心接收计算出的干扰的第二信号处理中心。

    System and Method for an Asynchronous Processor with Scheduled Token Passing
    10.
    发明申请
    System and Method for an Asynchronous Processor with Scheduled Token Passing 有权
    具有计划令牌传递的异步处理器的系统和方法

    公开(公告)号：US20150074382A1

    公开(公告)日：2015-03-12

    申请号：US14325117

    申请日：2014-07-07

    Applicant: Futurewei Technologies, Inc.

    Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

    IPC: G06F9/48

    CPC classification number: H04L12/433 ,  G06F9/3871 ,  G06F15/16

    Abstract: Embodiments are provided for adding a token jump logic to an asynchronous processor with token passing. The token jump logic allows token forward jumps and token backward jumps over a cascade of token processing logics in the processor. An embodiment method includes determining, using a token jump logic coupled to a cascade of token processing logics, whether to administer a token forward jump or a token backward jump of a token signal passing through the token processing logics. The token forward jump and token backward jump allow the token signal to skip one or more token processing logics in the cascade. The method further includes monitoring, for each of the token processing logics, a polarity status of a token sense logic, and inverting the polarity status according to the determination at the token jump logic.

    Abstract translation: 提供了实施例，用令牌传递将令牌跳转逻辑添加到异步处理器。 令牌跳转逻辑允许在处理器中的令牌处理逻辑级联的令牌向前跳跃和令牌向后跳转。 实施例方法包括使用耦合到令牌处理逻辑的级联的令牌跳转逻辑来确定是否管理通过令牌处理逻辑的令牌信号的令牌前向跳转或令牌反向跳转。 令牌向前跳转和令牌反向跳转允许令牌信号跳过级联中的一个或多个令牌处理逻辑。 该方法还包括针对令牌处理逻辑中的每一个监视令牌检测逻辑的极性状态，以及根据令牌跳转逻辑处的确定来反转极性状态。

Patent Agency Ranking