公开(公告)号：US20150074374A1

公开(公告)日：2015-03-12

申请号：US14480573

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Qifan Zhang ,  Wuxian Shi ,  Yiqun Ge ,  Tao Huang ,  Wen Tong

IPC: G06F9/30 ,  G06F15/78

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

Abstract translation: 包括异步标量处理器和耦合到标量处理器的异步向量处理器的异步处理系统。 异步标量处理器被配置为对输入数据执行处理功能并输出指令。 异步向量处理器被配置为响应于从标量处理器接收的非常长的指令字（VLIW）执行处理功能。 VLIW包括第一部分和第二部分，至少第一部分包括矢量指令。

公开(公告)号：US08824603B1

公开(公告)日：2014-09-02

申请号：US13782328

申请日：2013-03-01

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Qifan Zhang ,  Peter Man Kin Sinn

IPC: H04L27/06

CPC classification number: H04B7/0413 ,  G06F7/4818

Abstract: A method and a system is provided for Coordinate Rotation Digital Computer (CORDIC) based matrix inversion of input digital signal streams from multiple antennas using an bi-directional ring-bus architecture. The bi-directional ring bus includes a first ring bus having signals flow in a clockwise direction, and a second ring bus having signals flow in a counter-clockwise direction. An I/O controller is coupled to the first and the second ring bus, respectively. A plurality of processing elements (PEs), where each of the plurality of PEs is coupled to the first and the second ring bus, respectively, wherein each of the plurality of PEs includes at least one CORDIC core for performing CORDIC iterations on the plurality of input digital stream signals to produce inversed matrix signals.

Abstract translation: 提供了一种用于使用双向环形总线架构从多个天线输入数字信号流的坐标旋转数字计算机（CORDIC）矩阵求逆的方法和系统。 双向环形总线包括具有沿顺时针方向流动的信号的第一环形总线和具有逆时针方向的信号的第二环形总线。 I / O控制器分别耦合到第一和第二环形总线。 多个处理元件（PE），其中所述多个PE中的每一个分别耦合到所述第一和第二环形总线，其中所述多个PE中的每一个包括用于在所述多个PE中执行CORDIC迭代的至少一个CORDIC内核 输入数字流信号以产生反相矩阵信号。

公开(公告)号：US20150074680A1

公开(公告)日：2015-03-12

申请号：US14480561

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Qifan Zhang ,  Yiqun Ge ,  Wuxian Shi ,  Tao Huang ,  Wen Tong

IPC: G06F9/50 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A method of operating a clock-less asynchronous processing system comprising a plurality of successive asynchronous processing components. The method comprises providing a first token signal path in the plurality of processing components to allow propagation of a token through the processing components. Possession of the token by one of the processing components enables the processing component to conduct a transaction with a resource component that is shared among the processing components. The method comprises propagating the token from one processing component to another processing component along the token signal path.

Abstract translation: 一种操作包括多个连续的异步处理组件的无时钟异步处理系统的方法。 该方法包括在多个处理组件中提供第一令牌信号路径以允许令牌通过处理组件传播。 通过其中一个处理组件拥有令牌使处理组件能够与处理组件之间共享的资源组件进行交易。 该方法包括沿令牌信号路径将令牌从一个处理组件传播到另一个处理组件。

公开(公告)号：US20150074380A1

公开(公告)日：2015-03-12

申请号：US14480556

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Tao Huang ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Wen Tong

IPC: G06F9/38

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

Abstract translation: 一种包括多个并行异步处理逻辑电路的无时钟异步处理器，每个处理逻辑电路经配置以产​​生指令执行结果。 处理器包括耦合到每个处理逻辑电路的异步指令调度单元，所述指令调度单元被配置为从存储器接收多个指令，并向每个处理逻辑电路发送单独的指令。 处理器包括耦合到每个处理逻辑电路的输出的交叉开关和分配单元，该交叉开关被配置为存储指令执行结果。

公开(公告)号：US20150074378A1

公开(公告)日：2015-03-12

申请号：US14480541

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/3838 ,  G06F9/3871

Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

Abstract translation: 为具有异构处理器的异步处理器提供实施例。 在一个实施例中，用于异步处理器的装置包括被配置为缓存指令的存储器以及被配置为处理指令的第一指令的第一单元（XU）。 所述装置还包括第二XU，其具有比所述第一XU更少受限于所述异步处理器的资源的访问，并被配置为处理所述指令的第二指令。 第二条指令需要访问资源。 所述装置还包括被配置为对所述第一指令和所述第二指令进行解码并且向所述第一XU发出所述第一指令的反馈引擎，以及被配置为向所述第二XU发送所述第二指令的调度器。

公开(公告)号：US20150074377A1

公开(公告)日：2015-03-12

申请号：US14477536

申请日：2014-09-04

Applicant: Futurewei Technologies, Inc.

Inventor： Wuxian Shi ,  Yiqun Ge ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/38

CPC classification number: G06F9/3871 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3885 ,  G06F9/4494

Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

Abstract translation: 为具有流水线算术和逻辑单元的异步处理器提供实施例。 异步处理器包括用于存储指令的非暂存存储器和布置在用于传递令牌的环形架构中的多个指令执行单元（XU）。 XU中的每一个包括被配置为从非暂时存储器获取第一指令并执行第一指令的逻辑电路。 逻辑电路还被配置为从非瞬时存储器获取第二指令，并且执行第二指令，而不管XU中的一个是否存储用于写入第一指令的令牌。 逻辑电路还被配置为在获取第二指令之后将第一指令写入非暂时存储器。

公开(公告)号：US20150074376A1

公开(公告)日：2015-03-12

申请号：US14480562

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F15/82 ,  G06F9/30

CPC classification number: G06F15/825 ,  G06F9/30058 ,  G06F9/38 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3871

Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

Abstract translation: 为使用主和辅助令牌的异步处理器提供实施例。 在一个实施例中，用于异步处理器的装置包括用于高速缓存多个指令的存储器，用于对来自存储器的指令进行解码的反馈引擎，以及耦合到反馈引擎并以令牌环结构排列的多个XU。 每个XU被配置为从反馈引擎接收指令的指令，并且接收与资源相关联的主令牌，并且还接收主令牌的辅助令牌。 在确定以异常顺序接收到辅助令牌和主令牌之后，XU被配置为检测与辅助令牌相关联的指令的操作状态，并且在根据操作状态确定所需动作时， 辅助令牌，执行所需的操作。

公开(公告)号：US20150082006A1

公开(公告)日：2015-03-19

申请号：US14477563

申请日：2014-09-04

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: G06F9/30

CPC classification number: G06F9/38 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3871

Abstract: Embodiments are provided for an asynchronous processor with an asynchronous Instruction fetch, decode, and issue unit. The asynchronous processor comprises an execution unit for asynchronous execution of a plurality of instructions, and a fetch, decode and issue unit configured for asynchronous decoding of the instructions. The fetch, decode and issue unit comprises a plurality of resources supporting functions of the fetch, decode and issue unit, and a plurality of decoders arranged in a predefined order for passing a plurality of tokens. The tokens control access of the decoders to the resources and allow the decoders exclusive access to the resources. The fetch, decode and issue unit also comprises an issuer unit for issuing the instructions from the decoders to the execution unit

Abstract translation: 为具有异步指令提取，解码和发布单元的异步处理器提供实施例。 异步处理器包括用于异步执行多个指令的执行单元，以及被配置用于对指令进行异步解码的读取，解码和发布单元。 获取，解码和发布单元包括支持获取，解码和发布单元的功能的多个资源，以及以预定顺序排列以传送多个令牌的多个解码器。 令牌控制解码器对资源的访问，并允许解码器独占访问资源。 提取，解码和发布单元还包括用于从解码器向执行单元发出指令的发行者单元

公开(公告)号：US20150074787A1

公开(公告)日：2015-03-12

申请号：US14480330

申请日：2014-09-08

Applicant: Futurewei Technologies, Inc.

Inventor： Yiqun Ge ,  Wuxian Shi ,  Qifan Zhang ,  Tao Huang ,  Wen Tong

IPC: H04L29/06

CPC classification number: G06F13/385

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

Abstract translation: 为具有分层令牌系统的异步处理器提供实施例。 异步处理器包括一组主处理单元，其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。 异步处理器还包括一组辅助单元，其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。 主令牌系统的令牌集合包括在主处理单元组中消耗的令牌，并被指定用于触发该次要单元组中的辅助令牌系统。

公开(公告)号：US20150074446A1

公开(公告)日：2015-03-12

申请号：US14480531

申请日：2014-09-08

Applicant: Futurewei Technologies Inc.

Inventor： Wen Tong ,  Yiqun Ge ,  Qifan Zhang ,  Wuxian Shi ,  Huang Tao

IPC: G06F1/08

CPC classification number: G06F9/30145 ,  G06F1/08 ,  G06F1/10 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3871 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F9/5011 ,  G06F15/8007 ,  G06F15/8053 ,  G06F15/8092 ,  G06F2009/3883

Abstract: A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

Abstract translation: 无时钟异步处理电路或系统利用自定时发生器来调整电路/系统中处理周期所需/允许的处理延迟（等待时间）。 自定时发生器的定时可根据各种参数动态调整。 这些参数可以包括处理指令，操作码信息，由电路/系统执行的处理类型或整体期望的处理性能。 还可以调整延迟以改变处理性能，包括功耗，速度等。