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    Readout system for visually displaying stored data
    13.
    发明授权
    Readout system for visually displaying stored data 失效
    用于可视显示存储数据的读出系统

    公开(公告)号：US3651481A

    公开(公告)日：1972-03-21

    申请号：US3651481D

    申请日：1968-02-29

    Applicant: GEN ELECTRIC

    Inventor： EVANS JOHN T ,  KELLING LEROY U C

    IPC: G05B19/4069 ,  G09G3/04 ,  G06F7/30 ,  G06F13/02

    CPC classification number: G05B19/4069 ,  G05B2219/34239 ,  G05B2219/35481 ,  G09G3/04

    Abstract: A system for visually displaying interlaced data stored in a recirculating delay line. The stored data is in six functions, each function comprising three eight digit words. Data within each function is interlaced by presenting the least significant digit of all three words, followed by the next to least significant digit of all three words and so on. The data display may be single selected words or may comprise display of particular words in predetermined sequence. Sequential display of all three words in selected functions is accomplished by providing a three bit recirculating shift register. The sequencing rate is controlled by a variable frequency oscillator. It is also possible to sequentially select the data associated with each letter address. This is accomplished by way of a second recirculating shift register whose sequencing rate is also controlled by the variable frequency oscillator. As the data is selected, it is fed into a third shift register where it is stored in binary coded decimal. A BCD to decimal converter converts the contents of the third shift register to decimal format. THe output of the BCD to decimal converter feeds the display device. The rate at which the contents of the third shift register are ''''updated'''' may also be controlled by providing an oscillator whose frequency determines the ''''update'''' rate.

    Abstract translation: 用于可视地显示存储在再循环延迟线中的隔行扫描数据的系统。 存储的数据有六个功能，每个功能包括三个八位数字。 每个功能中的数据通过呈现所有三个字的最低有效数字，随后是所有三个字的下一个最低有效数字，以此类推。 数据显示可以是单个选择的单词，或者可以包括以预定顺序显示特定单词。 通过提供三位循环移位寄存器来实现所选功能中所有三个字的顺序显示。 排序速率由可变频率振荡器控制。 也可以顺序地选择与每个字母地址相关联的数据。 这通过第二再循环移位寄存器来实现，其排序率也由可变频率振荡器控制。 当数据被选择时，它被馈送到第三移位寄存器，其中以二进制编码十进制存储。 BCD到十进制转换器将第三移位寄存器的内容转换为十进制格式。 BCD到十进制转换器的输出为显示设备供电。 也可以通过提供频率确定“更新”速率的振荡器来控制第三移位寄存器的内容“更新”的速率。

    Serial bcd adder/subtracter utilizing interlaced data
    15.
    发明授权
    Serial bcd adder/subtracter utilizing interlaced data 失效
    使用相互连接的数据的串行BCD ADDER / SUBTRACTER

    公开(公告)号：US3571582A

    公开(公告)日：1971-03-23

    申请号：US3571582D

    申请日：1968-02-29

    Applicant: GEN ELECTRIC

    Inventor： KELLING LEROY U C

    IPC: G06F7/495 ,  G06F7/50

    CPC classification number: G06F7/495

    Abstract: A serial digital adding/subtracting arrangement for binary coded decimal data presented in interlaced format. The input data comprises a series of multidigit decimal words interlaced by serially presenting the least significant digit of each word in predetermined sequence, followed by the next digit of each word similarly interlaced, and so on throughout the data. The adding/subtracting utilizes two full adder/subtracters, the first for adding or subtracting the input data, the second for adding or subtracting six to or from the sum or difference generated by the first. The presence of a carry from either adder during the fourth bit time indicates the need for a radix correction from binary to decimal in which case the output of the second adder is selected. Several shift registers, one associated with each word, are provided to store the interdigital carries associated with that word during the processing of other words through the system.

    Spindle speed control monitor
    16.
    发明授权
    Spindle speed control monitor 失效
    主轴速度控制监视器

    公开(公告)号：US3564368A

    公开(公告)日：1971-02-16

    申请号：US3564368D

    申请日：1968-01-10

    Applicant: GEN ELECTRIC

    Inventor： KELLING LEROY U C

    IPC: G05B19/33 ,  H02P23/00 ,  H02P5/06

    CPC classification number: G05B19/33 ,  G05B2219/41364 ,  H02P23/186 ,  Y10S388/902 ,  Y10S388/909 ,  Y10S388/912

    Abstract: THE FEEDBACK WAVEFORM IN A CLOSED LOOP POSITION CONTROLLING SYSTEM FOR CONTROLLING THE SPEED OF A SPINDLE IS USED TO GENERATE AN ENVELOPE WAVEFORM WHICH SETS THE LIMITS OF THE SYSTEM RESPONSE. IN THE CLOSED LOOP POSITION CONTROLLING SYSTEM, THE SPEED OF THE SPINDLE MOTOR IS CONTROLLED BY A TRAIN OF VELOCITY PULSES. THE VELOCITY PULSES ARE ACCUMULATED BY A COMMAND PHASE COUNTER WHOSE OUTPUT PHASE IS COMPARED WITH THE PHASE OF A FEEDBACK WAVEFORM WHOSE PHASE IS RELATED TO THE SPINDLE MOTOR ROTATIONAL POSITIN. THE PHASE DIFFERENCE DRIVES THE MOTOR IN A DIRECTION TO REDUCE THE PHASE DIFFERENCE TO ZERO. AT THE START OF EACH SPINDLE SPEED MONITORING CYCLE, A FAST AND SLOW PHASE COUNTER ARE CLEARED, PRESET AND STARTED COUNTING BY ONE OF THE FEEDBACK PULSES. THE PRESETTING OPERATION CAUSES THE INITIAL PHASE PRESET OF THESE COUNTERS TO STRADDLE THE PHASE OF THE FEEDBACK PULSE. THE FAST COUNTER PROVIDES AN OUTPUT WAVEFORM WHICH HAS ITS PHASE ADVANCING SLIGHTLY FASTER THAN THE PHASE OF THE OUTPUT

    SIGNAL OF THE COMMAND PHASE COUNTER. THE SLOW COUNTER PROVIDES AN OUTPUT WAVEFORM WHICH HAS ITS PHASE ADVANCING SLIGHTLY SLOWER THAN THE PHASE OF THE OUTPUT SIGNAL OF THE COMMAND PHASE COUNTER. THE TERMINATION OF EACH FEEDBACK PULSE IS COMPARED IN PHASE WITH THE OUTPUTS FROM THE FAST AND SLOW COUNTERS, AND AN INDICATION IS PROVIDED IF THE FEEDBACK WAVEFORM FALLS OUTSIDE OF THE LIMITS SET BY THE FAST AND SLOW COUNTER WAVEFORMS.

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