公开(公告)号：US09384318B2

公开(公告)日：2016-07-05

申请号：US14263340

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Guoxiang Ning ,  Paul Ackmann ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Abstract translation: 公开了用于使OPC模型能够解决掩模中的错误的方法和装置。 实施例包括：确定电路设计的图形层; 估计在制造的电路中指示用于形成图案化层的制造掩模的掩模角舍入误差的穿透比; 以及基于所述穿透比，由处理器确定所述电路设计的光学邻近校正的补偿度量。

公开(公告)号：US20170235866A1

公开(公告)日：2017-08-17

申请号：US15585972

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

公开(公告)号：US09672313B2

公开(公告)日：2017-06-06

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20160291457A1

公开(公告)日：2016-10-06

申请号：US14674157

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

IPC: G03F1/36 ,  H01L21/768 ,  G03F7/30

CPC classification number: G03F1/36

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

公开(公告)号：US20150006138A1

公开(公告)日：2015-01-01

申请号：US13932141

申请日：2013-07-01

Applicant: Globalfoundries Inc.

Inventor： Guo Xiang Ning ,  Fang Hong Gn ,  Paul Ackmann ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G03F7/70441 ,  G03F1/36

Abstract: Approaches for simulating a photolithographic process are provided. Specifically, provided is an optical proximity correction (OPC) model that includes kernel parameters corresponding to inter-layer activity and an etch process for a connecting via of an integrated circuit (IC). A resultant intensity is determined for a corresponding plurality of process variations corresponding to the interlayer activity and the etch process. As such, the OPC model considers both interlay activity and etch process.

Abstract translation: 提供了用于模拟光刻工艺的方法。 具体地，提供了包括对应于层间活动的核参数和用于集成电路（IC）的连接通路的蚀刻处理的光学邻近校正（OPC）模型。 对于与层间活性和蚀刻工艺相对应的相应多个工艺变化确定合成强度。 因此，OPC模型考虑了interlay活动和蚀刻过程。