公开(公告)号：US09535319B2

公开(公告)日：2017-01-03

申请号：US14674157

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

IPC: G03F1/36 ,  G03F7/30 ,  H01L21/768

CPC classification number: G03F1/36

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

公开(公告)号：US20170235866A1

公开(公告)日：2017-08-17

申请号：US15585972

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

公开(公告)号：US20160291457A1

公开(公告)日：2016-10-06

申请号：US14674157

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

IPC: G03F1/36 ,  H01L21/768 ,  G03F7/30

CPC classification number: G03F1/36

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

公开(公告)号：US09817940B2

公开(公告)日：2017-11-14

申请号：US15585972

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

公开(公告)号：US20160328510A1

公开(公告)日：2016-11-10

申请号：US14703179

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract translation: 一种方法包括接收包括多个层的集成电路的布局，选择一个层并提供一个或多个瓦片数值。 基于瓦片数值将集成电路的管芯区域划分为多个瓦片。 确定在布局的基础上，如果瓦片中所选择的一个层的一部分具有用于包含测试单元或虚拟单元的可用空间，并且将指示结果的标签分配给 瓦。 根据所分配的标签确定是否满足一个或多个空间可用性标准，并且如果满足，则将标签用于在布局中放置一个或多个测试单元和一个或多个虚拟单元中的至少一个 。

公开(公告)号：US09672312B2

公开(公告)日：2017-06-06

申请号：US14703179

申请日：2015-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.