公开(公告)号：US20150076653A1

公开(公告)日：2015-03-19

申请号：US14028724

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。

公开(公告)号：US20150050792A1

公开(公告)日：2015-02-19

申请号：US13965258

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth B. Samavedam ,  Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Nicholas V. LiCausi ,  Daniel Pham

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

Abstract translation: 公开了形成窄隔离区域的方法。 狭窄的隔离区域可以用作非常窄的扩散断裂，适用于3D FinFET技术。 在半导体衬底上形成衬垫氮化物层。 在衬垫氮化物层中形成腔体。 在腔中沉积保形间隔衬垫。 然后，各向异性蚀刻工艺在半导体衬底中形成沟槽。 沟槽足够窄，使得虚拟栅极完全覆盖沟槽。 然后可以在与虚拟栅极相邻的位置形成外延应力区域。 沟槽足够窄，使得在外延应力区域和沟槽之间存在间隙。