公开(公告)号：US20150311308A1

公开(公告)日：2015-10-29

申请号：US14261559

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。

公开(公告)号：US10141414B1

公开(公告)日：2018-11-27

申请号：US15784500

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/78

Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.

公开(公告)号：US09577042B1

公开(公告)日：2017-02-21

申请号：US14825949

申请日：2015-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Rohit Galatage

IPC: H01L29/205 ,  H01L29/165 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.

Abstract translation: 完全III-V半导体或Si基晶体管的源极/漏极包括可以与沟道晶格匹配的底部阻挡层，宽带隙III-V材料的下层和较窄带隙的顶层 III-V材料，下层和顶层之间的组成渐变层从宽带隙材料逐渐过渡到窄带隙材料。