公开(公告)号：US07589019B2

公开(公告)日：2009-09-15

申请号：US11443432

申请日：2006-05-31

申请人： Dominik Olligs ,  Veronika Polei

发明人： Dominik Olligs ,  Veronika Polei

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L27/115

摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.

摘要翻译： 存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。 每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。 存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。 第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

公开(公告)号：US07368350B2

公开(公告)日：2008-05-06

申请号：US11313247

申请日：2005-12-20

申请人： Dominik Olligs ,  Torsten Mueller ,  Karl-Heinz Kuesters ,  Veronika Polei ,  Thomas Mikolajick ,  Josef Willer

发明人： Dominik Olligs ,  Torsten Mueller ,  Karl-Heinz Kuesters ,  Veronika Polei ,  Thomas Mikolajick ,  Josef Willer

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/76831 ,  H01L21/76888 ,  H01L21/76897 ,  H01L27/11568

摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

摘要翻译： 公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。 提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。 在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。 另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。 接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

公开(公告)号：US20070278546A1

公开(公告)日：2007-12-06

申请号：US11443432

申请日：2006-05-31

申请人： Dominik Olligs ,  Veronika Polei

发明人： Dominik Olligs ,  Veronika Polei

IPC分类号： H01L29/94

CPC分类号： H01L27/115

摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.

摘要翻译： 存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。 每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。 存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。 第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

公开(公告)号：US20070200149A1

公开(公告)日：2007-08-30

申请号：US11364586

申请日：2006-02-28

申请人： Veronika Polei ,  Dominik Olligs

发明人： Veronika Polei ,  Dominik Olligs

IPC分类号： H01L29/80

CPC分类号： H01L21/0206 ,  H01L21/28061 ,  H01L21/32139 ,  H01L29/4941

摘要： A layer sequence with lateral boundaries, especially a gate electrode stack, comprises a cover layer between a metal layer and a top layer that is provided as a hardmask. The cover layer, which is preferably polysilicon, enables the application of a cleaning agent to remove a resist layer, clean the hardmask and remove deposits of the material of the top layer produced in the structuring of the hardmask, before the layer sequence is structured using the hardmask. The cover layer protects the metal layer, which could otherwise be damaged by the cleaning agent.

摘要翻译： 具有横向边界的层序列，特别是栅极电极堆叠，包括在作为硬掩模提供的金属层和顶层之间的覆盖层。 优选多晶硅的覆盖层能够在层序列结构化之前使用清洁剂去除抗蚀剂层，清洁硬掩模并去除硬质掩模的结构中产生的顶层材料的沉积物 硬掩模 覆盖层保护金属层，否则可能由清洁剂损坏。

公开(公告)号：US20070141799A1

公开(公告)日：2007-06-21

申请号：US11313247

申请日：2005-12-20

申请人： Dominik Olligs ,  Torsten Mueller ,  Karl-Heinz Kuesters ,  Veronika Polei ,  Thomas Mikolajick ,  Josef Willer

发明人： Dominik Olligs ,  Torsten Mueller ,  Karl-Heinz Kuesters ,  Veronika Polei ,  Thomas Mikolajick ,  Josef Willer

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76831 ,  H01L21/76888 ,  H01L21/76897 ,  H01L27/11568

摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

摘要翻译： 公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。 提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。 在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。 另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。 接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

公开(公告)号：US20070057318A1

公开(公告)日：2007-03-15

申请号：US11228036

申请日：2005-09-15

申请人： Lars Bach ,  Dominik Olligs ,  Torsten Mueller ,  Veronika Polei

发明人： Lars Bach ,  Dominik Olligs ,  Torsten Mueller ,  Veronika Polei

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7923 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352

摘要： A semiconductor substrate is provided with a recess. A memory layer or memory layer sequence is applied to sidewalls and the bottom of the recess. The memory layer is formed into two separate portions at opposite sidewalls of the recess either by reducing the memory layer to sidewall spacers or by forming sidewall spacers and removing portions of the memory layer that are not covered by the spacers. A gate electrode is applied into the recess, and source/drain regions are formed by an implantation of doping atoms adjacent to the sidewalls of the recess and the remaining portions of the memory layer. The memory layer can especially be a dielectric material suitable for charge-trapping.

摘要翻译： 半导体衬底设置有凹部。 存储层或存储器层序列被施加到凹槽的侧壁和底部。 存储层通过将存储层减小到侧壁间隔物或通过形成侧壁间隔物和去除未被间隔物覆盖的存储层的部分而在凹槽的相对侧壁处形成两个分开的部分。 栅电极被施加到凹槽中，并且通过注入与凹槽的侧壁和存储层的其余部分相邻的掺杂原子来形成源/漏区。 存储层可以特别地是适用于电荷俘获的电介质材料。

公开(公告)号：US20060024889A1

公开(公告)日：2006-02-02

申请号：US11194059

申请日：2005-07-29

申请人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

发明人： Achim Gratz ,  Mayk Roehrich ,  Veronika Polei

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device can be fabricated by forming a floating gate layer over a semiconductor body. The floating gate layer is at least partially arranged over an insulation region in the semiconductor body. The floating gate layer is patterned to expose a portion of the insulation region. A recess is formed in a portion of the insulation region exposed by the patterned floating gate layer. A conductor is deposited within the recess. The conductor serves as a buried bitline. An insulator can then be formed within the recess over the conductor.

公开(公告)号：US06709876B2

公开(公告)日：2004-03-23

申请号：US10215226

申请日：2002-08-08

申请人： Veronika Polei ,  Martin Welzel

发明人： Veronika Polei ,  Martin Welzel

IPC分类号： H01L2100

CPC分类号： H01L22/26 ,  G03F7/42

摘要： In a method for removing an organic material from semiconductor devices, at least one semiconductor device is inserted into a so-called piranha bath. Measurement data are processed to get a data curve for measuring a concentration of at least one reaction product. The measurement data is queried for at least one of a turning point, a local maximum point or a local minimum point of the curve each being significantly different from signal noise after removing the semiconductor device from the fluid. With the information it is decided whether further processing of the semiconductor device is needed. The method is suitable for detecting an incomplete removal of organic material, i.e. photoresist deposited on the processed semiconductor device.

摘要翻译： 在从半导体器件中去除有机材料的方法中，至少一个半导体器件插入所谓的食人鱼浴中。 处理测量数据以获得用于测量至少一种反应产物浓度的数据曲线。 在将半导体器件从流体中除去之后，对于曲线的转折点，局部最大点或局部最小点中的至少一个与信号噪声显着不同，查询测量数据。 利用该信息，决定是否需要进一步处理半导体器件。 该方法适用于检测有机材料的不完全去除，即沉积在经处理的半导体器件上的光致抗蚀剂。