公开(公告)号：US20240131198A1

公开(公告)日：2024-04-25

申请号：US18225564

申请日：2023-07-24

Applicant: Davide Brambilla ,  Samuel Babity

Inventor： Davide Brambilla ,  Samuel Babity

IPC: A61K49/00 ,  A61M37/00

CPC classification number: A61K49/0032 ,  A61K49/0006 ,  A61K49/0054 ,  A61M37/0015 ,  A61M2037/0061

Abstract: The present disclosure relates to ratiometric detection compositions comprising a reference dye and a sensor dye that are PEGylated dyes, and microneedles comprising said compositions. The present disclosure further relates to methods of ratiometric detection/measurement/monitoring of analytes in a subject using the ratiometric detection compositions of the present disclosure.

公开(公告)号：US06437606B1

公开(公告)日：2002-08-20

申请号：US09687145

申请日：2000-10-13

Applicant: Danilo Ranieri ,  Davide Brambilla ,  Edoardo Botti ,  Luca Celant

Inventor： Danilo Ranieri ,  Davide Brambilla ,  Edoardo Botti ,  Luca Celant

IPC: H03K522

CPC classification number: H03F1/52

Abstract: A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.

Abstract translation: 评估放大信道的输出节点上的偏移量的方法包括：生成逻辑信号，用于发信号通知具有超过关于零电平对称的允许电平的窗口的电平的偏移的存在。 窗口由负极限值和正极限值定义。 该方法包括通过向检测电路的输入施加具有一定频率的定时脉冲，感测定时脉冲的上升沿并设置双稳态电路，建立检测的间隔或相位，并将输出节点上的信号进行比较 放大器通道与允许值的窗口。 在初始设置之后，双稳态电路在允许值的窗口内的输出信号幅度出现之后被复位。 双稳态电路在检测阶段结束之前复位的故障发出过大的偏移。

公开(公告)号：US06429741B2

公开(公告)日：2002-08-06

申请号：US09880638

申请日：2001-06-12

Applicant: Davide Brambilla ,  Daniela Nebuloni ,  Mauro Cleris

Inventor： Davide Brambilla ,  Daniela Nebuloni ,  Mauro Cleris

IPC: H03F126

CPC classification number: H03F1/3217 ,  H03F1/34

Abstract: An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.

Abstract translation: 具有输入的放大器; 提供输出信号的输出和连接在输入和输出之间的反馈网络，以及失真检测电路。 反馈网络包括串联布置的第一和第二反馈元件，并且形成中间节点，在没有失真的情况下提供与输出信号同相的中间信号，并且在存在失真的情况下与输出信号相反。 失真检测电路包括相位比较电路，当相对于输出信号相位相反时，相位比较电路检测输出信号和中间信号的相位，并产生失真指示信号。

公开(公告)号：US5194821A

公开(公告)日：1993-03-16

申请号：US793628

申请日：1991-11-18

Applicant: Davide Brambilla ,  Guido Brasca ,  Edoardo Botti

Inventor： Davide Brambilla ,  Guido Brasca ,  Edoardo Botti

IPC: H03F1/02 ,  H03F3/20 ,  H03F3/30 ,  H03F3/68 ,  H03G3/30

CPC classification number: H03F1/0277 ,  H03F3/3081

Abstract: The amplifier comprises a first and a second amplifier block of opposite phase driven by a single input signal and having its outputs connected to the two terminals of a load. It also comprises circuit means to disable one of the said amplifier blocks when the absolute value of the input signal is less than a predetermined threshold level. A passive feedback system capable of maintaining the amplifier gain constant is located between the aforesaid terminals of the load and the inputs to the two amplifier blocks.

公开(公告)号：US20060022749A1

公开(公告)日：2006-02-02

申请号：US11022020

申请日：2004-12-23

Applicant: Fabio Chelli ,  Davide Brambilla

Inventor： Fabio Chelli ,  Davide Brambilla

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F1/32 ,  H03F3/3081 ,  H03F3/68 ,  H03F2200/03 ,  H03F2200/114 ,  H03F2203/45138

Abstract: A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.

Abstract translation: 共模控制电路减少了一对放大器的输出端的突变电压变化，这又降低了当馈送到音频系统的四个通道的信号之间的相关性减小时发生的EMI和失真。 共模控制电路为每个放大器产生作为当放大器切换到桥接配置时饱和的放大器的相应差分输入信号的饱和副本的参考电位。

公开(公告)号：US06384645B2

公开(公告)日：2002-05-07

申请号：US09824534

申请日：2001-04-02

Applicant: Davide Brambilla ,  Mauro Cleris

Inventor： Davide Brambilla ,  Mauro Cleris

IPC: H03K406

CPC classification number: H03K4/06 ,  H03K4/023

Abstract: An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch. A resistor of a much smaller value than the ratio between the period of the triangular signal and the capacitance of the storage capacitor of the first hold circuit is connected between the output of the second hold circuit and the input node.

Abstract translation: 用于产生小斜坡电压斜坡的集成电路包括用于产生周期性三角形电流信号的电路，以及用于在三角形信号的每个周期的开始处产生一定长度的脉冲，该脉冲远小于 三角形信号的周期。 在具有三角形电流信号的节点处输入控制回路，并在输出节点上产生所需的慢速电压斜坡。 控制回路包括通过由脉冲控制的第一开关耦合到输入节点的第一保持电路和跨导运算放大器，其输入分别耦合到输入节点和输出节点。 而且，控制回路包括第二保持电路，该第二保持电路通过相对于第一开关以互补方式控制的第二开关耦合到运算跨导放大器的输出端。 在第二保持电路的输出和输入节点之间连接有比三角形信号的周期和第一保持电路的存储电容的电容之间的比值小得多的电阻。

公开(公告)号：US6072359A

公开(公告)日：2000-06-06

申请号：US108081

申请日：1998-06-30

Applicant: Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

Inventor： Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

IPC: G05F3/26 ,  H03F3/345 ,  H03F3/343

CPC classification number: H03F3/345 ,  G05F3/267

Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit also has an impedance matching circuit connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Abstract translation: 具有可控频率响应的电流发生器电路具有由MOS晶体管形成的至少一个电流镜，其通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）由第一电流发生器 G1），并且具有用于在镜的输出端（OUT）上产生与参考电流（I1）成比例的镜像电流（Iout）的输出支路。 输入支路至少包括二极管连接的第一晶体管（M1），并且具有耦合到包括在输出支路中的第二晶体管（M2）的相应端子（Ga2）的控制端子（Ga1）。 根据本发明，镜电路还具有连接在第一和第二晶体管的控制端（Ga1和Ga2）两端的阻抗匹配电路，并被配置为在两端（Ga1和Ga2）处保持相同的电压值。 阻抗匹配电路具有可调节的输出阻抗，具体值低于没有该电路的值。 它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。 本发明同样适用于N沟道和P沟道MOS晶体管。 有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。