Abstract:
A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.
Abstract:
Data cells of plural classes are transferred from input ports to output ports through a switch by storing the cells at each input port in class-specific virtual output queues (VOQ) within sets of VOQs associated with output ports, and providing credits to VOQs according to class-associated guaranteed bandwidths. When a cell is received at a VOQ having credits, a high-priority request for transfer is generated. If a cell is received at a VOQ that does not have any available credits, a low-priority request for transfer is generated. In response to requests, grants are issued to VOQ sets without regard to class, high-priority requests being favored over low-priority requests. When a grant is received for a particular VOQ set, an arbitrator selects a VOQ from the set, giving priority to VOQs having credits over VOQs without credits, and a cell from the selected VOQ is transferred. Requests generated from all input ports are forwarded to a central scheduler associated with a switch fabric slice, the central scheduler issuing the grants. The switch fabric may comprise multiple slices and a central scheduler, across which requests may be distributed in parallel, for example, the switch fabric slices being selected in a fixed order. While all high-priority requests are granted, low priority requests may be granted by the central scheduler according to a weighted fair share policy.
Abstract:
A novel protocol for scheduling of packets in high-speed cell based switches is provided. The switch is assumed to use a logical cross-bar fabric with input buffers. The scheduler may be used in optical as well as electronic switches with terabit capacity. The proposed round-robin greedy scheduling (RRGS) achieves optimal scheduling at terabit throughput, using a pipeline technique. The pipeline approach avoids the need for internal speedup of the switching fabric to achieve high utilization. A method for determining a time slot in a N×N crossbar switch for a round robin greedy scheduling protocol, comprising N logical queues corresponding to N output ports, the input for the protocol being a state of all the input-output queues, output of the protocol being a schedule, the method comprising: choosing input corresponding to i=(constant-k−1)mod N, stopping if there are no more inputs, otherwise choosing the next input in a round robin fashion determined by i=(i+1)mod N; choosing an output j such that a pair (i,j) to a set C={(i,j)| there is at least one packet from I to j}, if the pair (i,j) exists; removing i from a set of inputs and repeating the steps if the pair (i,j) does not exist; removing i from the set of inputs and j from a set of outputs; and adding the pair (i,j) to the schedule and repeating the steps.
Abstract:
A large capacity ATM core switch architecture is disclosed, which supports multiple traffic classes and quality-of-service (QoS) guarantees. The switch supports both real-time traffic classes with strict QoS requirements, e.g., CBR and VBR, and non-real-time traffic classes with less stringent requirements, e.g., ABR and UBR. The architecture also accommodates real-time and non-real-time multicast flows in an efficient manner. The switch consists of a high-speed core module that interconnects input/output modules with large buffers and intelligent scheduling/buffer management mechanisms. The scheduling can be implemented using a novel dynamic rate control, which controls internal congestion and achieves fair throughput performance among competing flows at switch bottlenecks. In the dynamic rate control scheme, flows are rate-controlled according to congestion information observed at bottleneck points within the switch. Each switch flow is guaranteed a minimum service rate plus a dynamic rate component which distributes any unused bandwidth in a fair manner.
Abstract:
A scheme for determining the usage parameter control (UPC) values for an arbitrary traffic source from observations of its emitted cell stream is disclosed. The UPC values are used in a traffic shaping mechanism based on a dual leaky bucket, which shapes the cell stream by either discarding or delaying cells. The choice of UPC values is a function of the statistical characteristics of the observed cell stream; the user's tolerance for delay prior to the network access point; and the cost incurred on the network side. The chosen UPC values are then negotiated with the network. The source traffic characteristics may change dramatically over time, making the initially negotiated UPC descriptor inappropriate for the entire traffic stream. Hence, a method is disclosed for dynamically renegotiating UPC parameters whenever a predetermined change in traffic characteristics is detected. This method for real-time estimation and dynamic renegotiation of UPC parameters is the basis for a self-contained module which allows the source to make efficient use of the network resources.