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11.发明授权Method and apparatus for correlating computer system device physical location with logical address 失效将计算机系统设备物理位置与逻辑地址相关联的方法和装置
公开(公告)号：US6044411A
公开(公告)日：2000-03-28
申请号：US971687
申请日：1997-11-17
CPC分类号： G06F11/2289 , G06F12/0646
摘要： In an electronic system having at least one enclosure including at least one connecting board with at least one associated device coupled thereto, a respective physical location of each device is electronically determined, and an indication of each respective physical location is stored in memory disposed in the at least one enclosure. An operating system uses the stored physical location indication to correlate logical addresses to physical location.
摘要翻译： 在具有至少一个外壳的电子系统中，所述至少一个外壳包括至少一个具有耦合到其上的至少一个相关联的设备的连接板，电子地确定每个设备的相应物理位置，并将每个相应的物理位置的指示存储在设置在 至少一个外壳。 操作系统使用存储的物理位置指示将逻辑地址与物理位置相关联。
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12.发明授权公开(公告)号：US07225364B2
公开(公告)日：2007-05-29
申请号：US10388071
申请日：2003-03-13
IPC分类号： G06F11/00
CPC分类号： G06F13/12
摘要： A method, apparatus, and computer program product are provided for implementing a receive function over an interconnect network, such as InfiniBand. A virtual lane (VL) with a pending packet for a queue pair (QP) is selected. Then the pending packet is checked for an exceptional condition. Responsive to identifying the exceptional condition for the pending packet, a state bit is set for freezing the selected VL; and an interrupt is generated to firmware. Responsive to receiving the interrupt, the firmware determines a cause for freezing the selected VL and performs a responsive action. For example, the responsive action performed by firmware includes firmware performing an error recovery procedure (ERP) for the QP; firmware updating a state for the QP; or firmware performing application unique processing for the QP.
摘要翻译： 提供了一种用于通过诸如InfiniBand的互连网络实现接收功能的方法，装置和计算机程序产品。 选择具有用于队列对（QP）的等待分组的虚拟通道（VL）。 然后检查待处理的数据包是否有特殊情况。 响应于识别待处理分组的异常情况，设置状态位以冻结所选择的VL; 并向固件生成中断。 响应于接收中断，固件确定冻结所选VL的原因并执行响应动作。 例如，由固件执行的响应动作包括执行QP的错误恢复过程（ERP）的固件; 固件更新QP的状态; 或执行针对QP的应用唯一处理的固件。
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13.发明授权Method and apparatus for implementing global to local queue pair translation 有权用于实现全局到本地队列对转换的方法和装置公开(公告)号：US07212547B2
公开(公告)日：2007-05-01
申请号：US10360252
申请日：2003-02-06
CPC分类号： H04L49/90
摘要： A method, apparatus, and computer program product are provided for implementing global to local queue pair translation in a network transport layer. A global queue pair number is identified. The global queue pair number is translated to a smaller local queue pair number. The local queue pair number is used for storing local queue pair context data for outbound header generation and inbound header checking. Upper layers of the network protocol above the network transport layer are allowed to use the global queue pair numbers.
摘要翻译： 提供了一种用于在网络传输层中实现全局到本地队列对转换的方法，装置和计算机程序产品。 识别全局队列对号码。 全局队列对号被转换为较小的本地队列对。 本地队列对号用于存储用于出站报头生成和入站报头检查的本地队列对上下文数据。 允许网络传输层上方网络协议的上层使用全局队列对。
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14.发明授权公开(公告)号：US07024613B2
公开(公告)日：2006-04-04
申请号：US10359777
申请日：2003-02-06
CPC分类号： H04L49/901 , H04L49/90
摘要： A method, apparatus and computer program product are provided for implementing a transmit queue. A queue pair context memory is provided for storing a set of pointers for each queue pair. The set of pointers are used to control the transmit queue for receiving, processing, and sending messages. Responsive to identifying an error for a queue pair, a limit pointer enable bit and a limit pointer to identify a last request for processing after the error are stored in the queue pair context memory for the queue pair.
摘要翻译： 提供了一种实现发送队列的方法，装置和计算机程序产品。 提供队列对上下文存储器，用于存储每个队列对的一组指针。 指针集用于控制发送队列，用于接收，处理和发送消息。 响应于识别队列对的错误，限制指针使能位和限制指针，用于将错误后的最后一个处理请求标识存储在队列对的队列对上下文存储器中。
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15.发明授权Method and apparatus for implementing queue pair connection protection over infiniband 失效通过infiniband实现队列对连接保护的方法和装置公开(公告)号：US07266083B2
公开(公告)日：2007-09-04
申请号：US10374651
申请日：2003-02-26
申请人： Michael Joseph Carnevale , Charles Scott Graham , Brent William Jacobs , Daniel Frank Moertl , Timothy Jerry Schimke , Lee Anton Sendelbach
发明人： Michael Joseph Carnevale , Charles Scott Graham , Brent William Jacobs , Daniel Frank Moertl , Timothy Jerry Schimke , Lee Anton Sendelbach
IPC分类号： G01R31/08
CPC分类号： H04L43/0811 , H04L41/0663
摘要： A method, apparatus and computer program product are provided for implementing queue pair connection protection over an interconnect network, such as InfiniBand. A message packet is received for a queue pair (QP) and the QP is checked for an imminent connection failure. Responsive to identifying an imminent connection failure, a special message processing mode is established for the QP. After the special message processing mode is established, packets of the message are received without establishing a message queue entry and without storing packet data.
摘要翻译： 提供了一种用于在互连网络（例如InfiniBand）上实现队列对连接保护的方法，装置和计算机程序产品。 接收到队列对（QP）的消息分组，并检查QP是否即将发生连接故障。 响应于识别即将发生的连接故障，为QP建立了特殊的消息处理模式。 在建立特殊消息处理模式之后，接收到消息的报文，而不建立消息队列条目，不存储分组数据。
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公开(公告)号：US06519718B1
公开(公告)日：2003-02-11
申请号：US09506783
申请日：2000-02-18
IPC分类号： H04L124
CPC分类号： H04L1/24 , G06F11/221
摘要： A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.
摘要翻译： 提供了一种用于实现外围组件互连（PCI）桥的错误注入的方法和装置。 用于实现外围组件互连（PCI）桥的错误注入的装置包括多个PCI总线和耦合到多个PCI总线的控制逻辑。 控制逻辑针对多个PCI总线的选定总线。 在所选择的总线上检测到命中。 响应于检测到的命中，在所选择的总线上注入错误。 对于检测到的预定义错误类型的命中，操作必须匹配所选的读取或写入，目标或主机命令类型，并且地址必须与未屏蔽的地址位匹配。 对于另一预定义的错误类型的检测到的命中，PCI数据总线也必须与取消掩码数据寄存器匹配。
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公开(公告)号：US06581129B1
公开(公告)日：2003-06-17
申请号：US09414339
申请日：1999-10-07
申请人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4027
摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.
摘要翻译： 公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。 主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。 检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。 模式适配器。
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18.发明授权Independent control of DMA and I/O resources for mixed-endian computing systems 失效混合端计算系统的DMA和I / O资源的独立控制
公开(公告)号：US5781763A
公开(公告)日：1998-07-14
申请号：US861914
申请日：1997-05-22
申请人： Bruce Leroy Beukema , Gary Scott Delp , Larry Wayne Loen , Daniel Frank Moertl , Michael R. Trombley
发明人： Bruce Leroy Beukema , Gary Scott Delp , Larry Wayne Loen , Daniel Frank Moertl , Michael R. Trombley
CPC分类号： G06F13/4013
摘要： A mixed-endian computer system enhanced to manage I/O DMA without a software DMA performance penalty. A mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian system, as enhanced, performs one of two well-defined DMA operations based on control bits either in the DMA control register or in a bit vector associated with each page of processor storage. This invention also describes means for treating I/O registers as if they were of the endian of the executing processor, instead of the more typical need to have the register operate in a particular endian.
摘要翻译： 增强了一种混合端计算机系统，可以管理I / O DMA，而不会造成DMA性能损失。 如果需要，混合端计算机系统可以根据任务改变任务的端序模式。 混合端系统（如增强型）基于DMA控制寄存器中的控制位或与每个处理器存储页相关联的位向量执行两个定义良好的DMA操作之一。 本发明还描述了用于处理I / O寄存器的装置，就像它们是执行处理器的端序一样，而不是更典型地需要使寄存器在特定的端序中操作。
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19.发明授权Method for implementing enhanced vertical ECC storage in a dynamic random access memory 失效在动态随机存取存储器中实现增强型垂直ECC存储的方法公开(公告)号：US07451380B2
公开(公告)日：2008-11-11
申请号：US11071086
申请日：2005-03-03
IPC分类号： G11C29/00
CPC分类号： G06F11/1044
摘要： A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.
摘要翻译： 提供了一种用于在动态随机存取存储器中实现增强的垂直ECC存储的方法和装置。 动态随机存取存储器（DRAM）被分成多个组。 每个组都驻留在DRAM行地址选通（RAS）页面中，从而可以访问组内的多个位置，而不会引起额外的RAS访问损失。 每个组在逻辑上分成多个段，用于存储具有用于存储数据段的ECC的至少一个段的数据。 对于写入操作，将数据写入数据段，然后将ECC用于数据写入ECC段。 对于读取操作，从ECC段读取ECC，然后从数据段读取数据。
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20.发明申请公开(公告)号：US20080239841A1
公开(公告)日：2008-10-02
申请号：US11693812
申请日：2007-03-30
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C11/401 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A method and calibration apparatus implement calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads. A calibration control is provided to enable calibration testing. A selected one of a received DQS signal and an internal Enable signal is driven onto a data mask (DQM) IO during a DRAM read for calibration testing. The received DQS signal and the internal Enable signal are used to adjust the Enable delay to generally center the preamble time at the DQS receiver.
摘要翻译： 一种方法和校准装置在同步动态随机存取存储器（DRAM）读取期间实现数据选通信号（DQS）采样的校准。 提供校准控制以实现校准测试。 在用于校准测试的DRAM读取期间，所接收的DQS信号和内部使能信号中选择的一个被驱动到数据掩码（DQM）IO上。 接收的DQS信号和内部使能信号用于调整使能延迟，以使DQS接收机的前导码时间大致居中。
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