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11.发明申请Method and Apparatus for High Performance Cache Translation Look-Aside Buffer TLB Lookups Using Multiple Page Size Prediction 失效使用多页面大小预测的高性能缓存翻译查看缓冲区TLB查找的方法和装置公开(公告)号：US20110320789A1
公开(公告)日：2011-12-29
申请号：US12821723
申请日：2010-06-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes.
摘要翻译： 一种具有处理器的计算机处理系统方法和装置，所述处理器采用多个用户程序之间的操作系统（O / S）多任务控制，并确保所述程序不相互干扰，所述计算处理系统具有分支多页大小 预测机构，其预测具有分支目标缓冲器（BTB）的处理流水线的指示的分支方向的分支方向和分支目标的分页目标，所述分支目标缓冲器（BTB）预测分支目标，所述分支预测机制存储最近使用的指令， 处理器，并且具有跟踪最近页面的翻译并支持多个页面大小的翻译后备缓冲器TLB机制。
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12.发明授权High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction 失效使用多页大小预测的高性能缓存翻译后备缓冲区（TLB）查找公开(公告)号：US08667258B2
公开(公告)日：2014-03-04
申请号：US12821723
申请日：2010-06-23
CPC分类号： G06F9/3806 , G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes.
摘要翻译： 一种具有处理器的计算机处理系统方法和装置，所述处理器采用多个用户程序之间的操作系统（O / S）多任务控制，并确保所述程序不相互干扰，所述计算处理系统具有分支多页大小 预测机构，其预测具有分支目标缓冲器（BTB）的处理流水线的指示的分支方向的分支方向和分支目标的分页目标，所述分支目标缓冲器（BTB）预测分支目标，所述分支预测机制存储最近使用的指令， 处理器，并且具有跟踪最近页面的翻译并支持多个页面大小的翻译后备缓冲器TLB机制。
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公开(公告)号：US08751747B2
公开(公告)日：2014-06-10
申请号：US12037829
申请日：2008-02-26
CPC分类号： G06F12/121
摘要： A method for managing cache memory including receiving an instruction fetch for an instruction stream in a cache memory, wherein the instruction fetch includes an instruction fetch reference tag for the instruction stream and the instruction stream is at least partially included within a cache line, comparing the instruction fetch reference tag to a previous instruction fetch reference tag, maintaining a cache replacement status of the cache line if the instruction fetch reference tag is the same as the previous instruction fetch reference tag, and upgrading the cache replacement status of the cache line if the instruction fetch reference tag is different from the previous instruction fetch reference tag, whereby the cache replacement status of the cache line is upgraded if the instruction stream is independently fetched more than once. A corresponding system and computer program product.
摘要翻译： 一种用于管理高速缓存存储器的方法，包括接收高速缓冲存储器中的指令流的指令取出，其中指令获取包括用于指令流的指令获取参考标签，并且指令流至少部分地包括在高速缓存行内， 指令获取参考标签到先前的指令获取参考标签，如果指令获取引用标签与先前的指令获取引用标签相同，则保持高速缓存行的高速缓存替换状态，并且如果高速缓存行的高速缓存替换状态 指令获取参考标签与先前的指令获取参考标签不同，从而如果指令流被独立地提取多次，则缓存行的高速缓存替换状态被升级。 相应的系统和计算机程序产品。
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14.发明申请PROGRAM STATUS WORD DEPENDENCY HANDLING IN AN OUT OF ORDER MICROPROCESSOR DESIGN 有权程序状态字依赖于处理订单微处理器设计公开(公告)号：US20110320782A1
公开(公告)日：2011-12-29
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
IPC分类号： G06F9/318
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译： 一种处理计算机程序指令的计算机实现方法。 该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。
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15.发明申请公开(公告)号：US20100064121A1
公开(公告)日：2010-03-11
申请号：US12208683
申请日：2008-09-11
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译： 解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。 在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用 多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。 然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。
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公开(公告)号：US20090070561A1
公开(公告)日：2009-03-12
申请号：US11852443
申请日：2007-09-10
申请人： Gregory W. Alexander
发明人： Gregory W. Alexander
IPC分类号： G06F9/40
CPC分类号： G06F9/4486
摘要： Illustrative embodiments provide a method for improved link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structures forming a common pool and an operation control table. Maintaining, within the common pool, a plurality of entries for a plurality of speculative instructions and a plurality of non-speculative instructions. And determining one speculative instruction to be a bad prediction speculative entry, identifying related entries to form a collection, and discarding the collection.
摘要翻译： 说明性实施例提供了一种用于使用重命名结构来改进链接栈错误预测分辨率的方法，用于跟踪链路栈处理，以便从误预测的函数返回中快速解决链路栈损坏。 该方法包括建立一组形成公共池的物理数据结构和操作控制表。 在公共池内维护多个投机指令和多个非投机指令的多个条目。 并确定一个推测性指令是不良预测推测条目，识别相关条目以形成集合，并丢弃收集。
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17.发明授权Program status word dependency handling in an out of order microprocessor design 有权程序状态字依赖处理在一个无序的微处理器设计公开(公告)号：US09075600B2
公开(公告)日：2015-07-07
申请号：US12822974
申请日：2010-06-24
申请人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
发明人： Gregory W. Alexander , Brian D. Barrick , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei , David A. Schroter
CPC分类号： G06F9/30101 , G06F9/3838 , G06F9/384
摘要： A computer implemented method of processing instructions of a computer program. The method comprises providing at least two copies of program status data; identifying a first update instruction of the instructions that writes to at least one field of the program status data; and associating the first update instruction with a first copy of the at least two copies of program status data.
摘要翻译： 一种处理计算机程序指令的计算机实现方法。 该方法包括提供程序状态数据的至少两个副本; 识别写入所述程序状态数据的至少一个字段的所述指令的第一更新指令; 以及将所述第一更新指令与所述至少两个程序状态数据副本的第一副本相关联。
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公开(公告)号：US20130339666A1
公开(公告)日：2013-12-19
申请号：US13524471
申请日：2012-06-15
申请人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
发明人： Gregory W. Alexander , Brian D. Barrick , Fadi Y. Busaba , Bruce C. Giamei , Edward T. Malley , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30043 , G06F9/3017 , G06F9/384
摘要： A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag.
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19.发明授权Error detection enhancement in a microprocessor through the use of a second dependency matrix 失效微处理器通过使用第二个依赖矩阵进行错误检测增强公开(公告)号：US07549095B1
公开(公告)日：2009-06-16
申请号：US12165355
申请日：2008-06-30
IPC分类号： H03M13/00
CPC分类号： G06F9/3859 , G06F9/3838 , G06F9/3855 , G06F9/3861 , G06F11/0721 , G06F11/0751
摘要： A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.
摘要翻译： 一种微处理器错误检测方法，包括提供主依赖矩阵，提供用于发布微操作的问题逻辑，提供包括主依赖矩阵的副本的辅依赖矩阵，提供结果可用向量，所述结果可用向量包括 接收跟踪的每个依赖关系的条目，从发出逻辑发出微操作的指示，读取对应于所发出的微操作的次要依赖矩阵行，检查所读取的微操作是否依赖于跟踪依赖性 通过确定从辅助依赖矩阵中读取的行中设置的任何位是否未被设置在辅助结果可用向量中，并且如果微操作被取消，则从发布逻辑接收指示。
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20.发明授权Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache 失效在指令高速缓存中发生错误的情况下，在预取缓冲区中选择指令时的零周期损失公开(公告)号：US07032097B2
公开(公告)日：2006-04-18
申请号：US10422808
申请日：2003-04-24
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3814
摘要： A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.
摘要翻译： 一种方法和处理器，用于在具有零循环损失的指令高速缓存中的未命中的情况下，在预取缓冲器中选择指令。 可以对从程序计数器检索的地址执行第一，第二和第三散列。 第一个散列地址可以用于索引到指令高速缓存。 第二个散列地址可以用于索引到预取缓冲区。 如果存储在指令高速缓存的有效地址阵列中的索引条目中的值不等于地址（指令高速缓存未命中）的第三散列值，则选择预取缓冲器中索引条目中的指令。 以这种方式，可以在具有零周期损失的指令高速缓存中的未命中的情况下在预取缓冲器中选择指令。
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