Galois field linear transformer trellis system
    11.
    发明授权
    Galois field linear transformer trellis system 失效
    伽罗瓦斯线性变压器网格系统

    公开(公告)号:US07693928B2

    公开(公告)日:2010-04-06

    申请号:US10753301

    申请日:2004-01-07

    IPC分类号: G06F15/00 H03M13/03 H04L5/12

    摘要: A Galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.

    摘要翻译: 伽罗瓦域线性变压器网格系统包括伽罗瓦域线性变压器矩阵; 输入选择电路,用于向矩阵提供一个或多个格状比特流中的多个输入比特和该矩阵的网格状态输出,以及用于配置该矩阵以执行该一矩阵的多周期伽罗瓦域变换的可编程存储装置 或更多的网格位流和网格状态输出,以在单个周期中提供多个网格输出通道符号和新的网格状态输出。

    Reconfigurable input Galois field linear transformer system
    12.
    发明授权
    Reconfigurable input Galois field linear transformer system 有权
    可重构输入伽罗瓦域线性变压器系统

    公开(公告)号:US07269615B2

    公开(公告)日:2007-09-11

    申请号:US10136170

    申请日:2002-05-01

    IPC分类号: G06F15/00

    CPC分类号: G06F7/724

    摘要: A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector circuit for selecting a storage plane representing a function for enabling the cells of the matrix which defines that function; and a reconfigurable input circuit for delivering input data to the enabled cells to apply that function to the input data.

    摘要翻译: 可重构输入伽罗瓦域线性变压器系统包括包含单元矩阵的伽罗瓦域线性变换器; 多个存储平面,用于存储表示多个不同功能的控制模式; 存储平面选择器电路,用于选择表示用于使能定义该功能的矩阵的单元的功能的存储平面; 以及可重配置输入电路,用于将输入数据传送到使能小区,以将该功能应用于输入数据。

    Channel adaptive iterative turbo decoder system and method
    13.
    发明申请
    Channel adaptive iterative turbo decoder system and method 有权
    信道自适应迭代turbo解码器系统及方法

    公开(公告)号:US20100070819A1

    公开(公告)日:2010-03-18

    申请号:US12283863

    申请日:2008-09-16

    IPC分类号: H03M13/05 G06F11/10

    摘要: A channel adaptive iterative turbo decoder for computing with MAP decoders a set of branch metrics for a window of received data, computing the forward and reverse recursive path state metrics and computing from the forward and reverse recursive path state metrics the log likelihood ratio for 1 and 0 and interleaving the decision bits; and identifying those MAP decoder decision bits which are non-convergent, computing a set of branch metrics for the received data, computing from the forward and reverse recursive path state metrics the log likelihood ratio (LLR) for 1 and 0 for each non-converged decision bit and interleaving the non-convergent decision bits.

    摘要翻译: 一种信道自适应迭代turbo解码器,用于使用MAP解码器计算接收数据窗口的一组分支度量,计算正向和反向递归路径状态度量,以及从正向和反向递归路径状态度量计算1和对数似然比 0并交错判决位; 并且识别那些不收敛的MAP解码器判定比特,计算接收数据的一组分支度量,从正向和反向递归路径状态度量,计算每个非收敛的对数似然比(LLR)1和0 判决位和交织非收敛判定位。

    Programmable data encryption engine
    14.
    发明授权
    Programmable data encryption engine 有权
    可编程数据加密引擎

    公开(公告)号:US07283628B2

    公开(公告)日:2007-10-16

    申请号:US10170267

    申请日:2002-06-12

    IPC分类号: H04L9/06 H04L9/18

    CPC分类号: H04L9/0625 H04L2209/12

    摘要: A programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm includes a Galois field linear transformer system (GFLT) responsive to a first input data block to execute an E permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle; and further includes a parallel look-up table system for implementing the unique data encryption standard selection function(s) and for condensing the second larger intermediate data block to a third data block similar to the first input data block in a second cycle and submitting it to the Galois field linear transformer system to execute a second permutation in a third cycle resulting in a data encryption standard cipher function of the first input data block.

    摘要翻译: 用于执行数据加密标准(DES)算法的密码函数的可编程数据加密引擎包括响应于第一输入数据块的伽罗瓦域线性变换器系统(GFLT),以执行E置换以获得扩展数据块并将其组合 具有在一个周期中获得第二较大中间数据块的密钥; 并且还包括用于实现唯一数据加密标准选择功能的并行查找表系统,并且用于在第二周期中将第二较大中间数据块与第一输入数据块类似的第三数据块进行聚合并将其提交 到Galois场线性变压器系统,以在第三周期中执行第二置换,得到第一输入数据块的数据加密标准密码函数。

    Parallel bit correlator
    15.
    发明授权
    Parallel bit correlator 有权
    并行位相关器

    公开(公告)号:US06738794B2

    公开(公告)日:2004-05-18

    申请号:US09829681

    申请日:2001-04-10

    IPC分类号: G06F1715

    摘要: A parallel bit correlator for recognizing a predetermined bit pattern including a predefined number m of bits in a stream of data bits including identifying successive sets of m bits in a stream of data bits and simultaneously comparing each of the sets of m bits to the predetermined bit pattern for detecting the presence of the predetermined bit pattern in the stream of data.

    摘要翻译: 一种并行比特相关器,用于识别包括在数据比特流中包括预定数量m比特的预定比特模式,包括识别数据比特流中的m比特的连续组,同时将m比特中的每一个与预定比特 用于检测数据流中预定位模式的存在的模式。

    Galois field linear transformer
    16.
    发明授权
    Galois field linear transformer 有权
    伽罗瓦域线性变压器

    公开(公告)号:US06587864B2

    公开(公告)日:2003-07-01

    申请号:US10051533

    申请日:2002-01-18

    IPC分类号: G06F700

    CPC分类号: G06F7/724

    摘要: A Galois field linear transformer includes a matrix responsive to a number of input bits in one or more bit streams and having a plurality of outputs providing the Galois field linear transformation of those bits; the matrix includes a plurality of cells, each cell including an exclusive OR logic circuit and AND logic circuit having an output connected to the exclusive OR logic circuit and an input connected to one of the input bits and a programmable storage device for providing an input to its associated AND logic circuit for setting the matrix to obtain a multi-cycle Galois field linear transformation of the inputs in a single cycle.

    摘要翻译: 伽罗瓦域线性变换器包括响应于一个或多个比特流中的多个输入比特的矩阵并且具有提供这些比特的伽罗瓦域线性变换的多个输出的矩阵; 矩阵包括多个单元,每个单元包括异或逻辑电路和与逻辑电路,该逻辑电路具有连接到异或逻辑电路的输出和连接到输入位之一的输入端和可编程存储器件,用于提供输入 其相关联的AND逻辑电路用于设置矩阵以在单个周期中获得输入的多周期伽罗瓦域线性变换。

    Multi-layer error correcting coding
    17.
    发明授权
    Multi-layer error correcting coding 有权
    多层纠错编码

    公开(公告)号:US09183079B2

    公开(公告)日:2015-11-10

    申请号:US14058048

    申请日:2013-10-18

    IPC分类号: H04L1/00 G06F11/10

    摘要: A transmission system may include a transformer, an adder, an encoder, and a transmitter. The transformer may segment and transform a data packet into segments. The adder may add a check code to each of the segments. The encoder may encode error correction to each of the segments with the added check code. A receiving system may include a receiver, a decoder, a checker, and a selector decoder. The decoder may decode error correction in each of the encoded segments. The checker may check the check code of the error corrected segments. The selector decoder may select at least one of the valid segments based upon the check code and transform the selected segments into a data packet.

    摘要翻译: 传输系统可以包括变压器,加法器,编码器和发射器。 变压器可以将数据包分段并转换成段。 加法器可以向每个段添加校验码。 编码器可以用添加的校验码对每个段进行纠错。 接收系统可以包括接收机,解码器,检验器和选择器解码器。 解码器可以解码每个编码段中的纠错。 检查员可以检查纠错段的检查码。 选择器解码器可以基于校验码来选择至少一个有效段,并将选择的段变换为数据分组。

    Programmable data encryption engine for advanced encryption standard algorithm
    18.
    发明授权
    Programmable data encryption engine for advanced encryption standard algorithm 有权
    可编程数据加密引擎,用于高级加密标准算法

    公开(公告)号:US07508937B2

    公开(公告)日:2009-03-24

    申请号:US10255971

    申请日:2002-09-26

    IPC分类号: H04K1/04

    CPC分类号: H04L9/0631 H04L2209/125

    摘要: A programmable data encryption engine for performing the cipher function of an advanced encryption standard (AES) algorithm includes a parallel look-up table system responsive in a first mode to a first data block for implementing an AES selection function and executing the multiplicative inverse in GF−1(28) and applying an affine over GF(2) transformation to obtain a subbyte transformation and in a second mode to the subbyte transformation to transform the subbyte transformation to obtain a shift row transformation, and a Galois field multiplier for transforming the shift row transformation to obtain a mix column transformation and add a round key resulting in an advanced encryption standard cipher function of the first data block.

    摘要翻译: 用于执行高级加密标准(AES)算法的加密功能的可编程数据加密引擎包括:以第一模式响应于第一数据块的并行查找表系统,用于实现AES选择功能并在GF中执行乘法逆 -1(28),并且在GF(2)变换上应用仿射以获得子字节变换,并且在第二模式中对子字节变换进行变换以变换子字节变换以获得移位行变换;以及用于变换移位的伽罗瓦域乘法器 行转换以获得混合列转换并添加一个循环密钥,产生第一数据块的高级加密标准密码函数。

    Method and system for fixed point fast fourier transform with improved SNR
    19.
    发明授权
    Method and system for fixed point fast fourier transform with improved SNR 有权
    用于具有改善的SNR的固定点快速傅立叶变换的方法和系统

    公开(公告)号:US07197525B2

    公开(公告)日:2007-03-27

    申请号:US10389655

    申请日:2003-03-14

    IPC分类号: G06F17/14 G06F7/38

    CPC分类号: G06F17/142

    摘要: A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage; scales the butterfly outputs of this stage from a predicted normalization scale factor to obtain the maximum butterfly output without overflow from this stage; determines from the butterfly outputs of this stage the minimum normalizing exponent for the butterfly outputs of this stage and predicts a normalization scale factor of the next stage from the minimum normalizing exponent of this stage and a stage guard scale value to obtain the maximum butterfly output without overflow from that next stage.

    摘要翻译: 在固定点快速傅里叶变换(FFT / IFFT)中提高信噪比(SNR)的系统和方法从采样输入和每个阶段的旋转因子蝶形输出产生; 将该阶段的蝶式输出从预测的归一化比例因子缩放,以获得没有溢出的最大蝶形输出; 从该阶段的蝶形输出确定该阶段的蝶形输出的最小归一化指数,并从该级的最小归一化指数预测下一级的归一化比例因子和级保护比例值,以获得没有 从下一个阶段溢出

    Reconfigurable parallel look up table system
    20.
    发明授权
    Reconfigurable parallel look up table system 有权
    可重构平行查询表系统

    公开(公告)号:US06829694B2

    公开(公告)日:2004-12-07

    申请号:US10131007

    申请日:2002-04-24

    IPC分类号: G06F1200

    CPC分类号: G06F9/345 G06F12/0207

    摘要: A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up tables; a column index register for storing a value representing the starting address of the look-up tables stored in the memory; and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the function of those values in each look-up table.

    摘要翻译: 可重新配置的并行查找表系统包括存储器; 存储在存储器中的多个查找表; 用于保存要在查找表中查找的值的行索引寄存器; 列索引寄存器,用于存储表示存储在存储器中的查找表的起始地址的值; 以及响应于列索引寄存器和行索引寄存器的地址转换电路,以同时为行索引寄存器中的每个值产生一个地址,以平行地定位每个查找表中的那些值的函数。