Abstract:
A built-in test circuit for testing a system timing margin of a processing device under-test is provided. The processing device includes a controller and first clock circuit, wherein the first clock circuit generates a first clock signal and the first clock signal is a main clock signal provided for operation of the processing device. The built-in test circuit includes a second clock circuit and a logic circuit, both of which are integrated with the processing device. The second clock circuit generates a second clock signal. The logic circuit processes the first and second clock signals and outputs a third clock signal. The third clock signal is used to determine system timing margin of the processing device.
Abstract:
A speed detection device includes a comparator module, a sensor lead with a node connected to the comparator module, and a limit set module. The limit set module is connected to the sensor lead node and to the comparator by an upper limit lead and a lower limit lead to provide upper and lower limits to the comparator that vary according to amplitude variation in voltage applied to the sensor lead.
Abstract:
A process for automated contact wetting in a sensor circuit includes generating a first current through a contact by sequencing a first circuit on, the first current exceeding a wetting threshold of the contact, and reducing current through the contact to a second current by sequencing a second circuit on, the second current being below the wetting threshold.
Abstract:
A built-in test system includes a control circuit, a transient voltage suppressor circuit, and a test switch. The control circuit is configured to receive a signal, and the transient voltage suppressor circuit includes first and second transient voltage suppressors connected in series between the signal and ground. The test switch is connected to selectively conduct current between the signal and a node between the first and second transient voltage suppressors. The control circuit is configured to control the test switch to test the first and second transient voltage suppressors.
Abstract:
A position sensor arrangement has a transformer based position sensor and a cable peaking correction apparatus. The cable peaking correction apparatus is coupled to at least one of a transformer based position sensor excitation input and the plurality of outputs from the transformer based position sensor.
Abstract:
Provided are embodiments for monitoring clock drift. Embodiments may include an XOR gate that is configured to receive a first clock signal from a first clock source and a second clock signal from a second clock source, wherein the XOR logic gate is further configured to generate a switching output based on an XOR operation of the first clock signal and the second clock signal, and a rising edge detector and a falling edge detector that are configured to detect a rising edge and a falling edge of the switching output. Embodiments may also include an AND gate that is configured to threshold compare the rising edge to a configurable threshold to determine if a fault condition exists indicating clock drift between the first clock signal and the second clock signal and provide an indication of the fault condition based at least in part on the comparison.
Abstract:
A system for determining a phase angle of a sensor waveform relative to an excitation waveform includes a controller that provides an excitation signal having an excitation frequency and a sample signal having four times the excitation frequency. An exciter provides a sinusoidal excitation waveform at the excitation frequency to a primary winding, thereby inducing a sensor waveform in a secondary winding. An analog-to-digital converter (ADC) measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and a wrap-around ADC measures a first and second voltage of the sinusoidal excitation waveform. The first voltage measurements are made at the same time, and the second voltage measurements are made at the same time. The system calculates the phase angle based on the first voltage measurements and the second voltage measurements.
Abstract:
A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the rotatable primary winding, a tertiary winding fixed relative to the rotatable primary winding and positioned π/2 radians out of phase with respect to the fixed secondary winding, an excitation module electrically connected to the rotatable primary winding and configured to provide an excitation signal to the rotatable primary winding where the excitation signal is an alternating current waveform having a fundamental frequency, and a controller electrically connected to the secondary winding and configured to sample a voltage across the secondary winding at 18 times the fundamental frequency, sample a voltage across the tertiary winding at 18 times the fundamental frequency, and determine an amplitude of the fundamental frequency based on the sampled voltages across the secondary and tertiary windings, where the alternating current waveform includes a third harmonic frequency.
Abstract:
A speed detection device includes a comparator module, a sensor lead with a node connected to the comparator module, and a limit set module. The limit set module is connected to the sensor lead node and to the comparator by an upper limit lead and a lower limit lead to provide upper and lower limits to the comparator that vary according to amplitude variation in voltage applied to the sensor lead.
Abstract:
An aircraft electrical system includes a controller system having a self-testing system configured to test an operability of a transient voltage suppression device. A single line communication bus is connected to a communications output of the controller. A first lightning protection device including the transient voltage suppression device is configured to protect the controller from transient voltages. An enable/disable circuit comprising a normally closed switch connects a low side of the lightning protection device to a neutral.