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公开(公告)号：US12085977B2
公开(公告)日：2024-09-10
申请号：US17553917
申请日：2021-12-17
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Gary L. Hess
CPC classification number: G06F1/08 , G06F1/12 , G06F9/30021 , G06F9/30029
Abstract: Provided are embodiments for monitoring clock drift. Embodiments may include an XOR gate that is configured to receive a first clock signal from a first clock source and a second clock signal from a second clock source, wherein the XOR logic gate is further configured to generate a switching output based on an XOR operation of the first clock signal and the second clock signal, and a rising edge detector and a falling edge detector that are configured to detect a rising edge and a falling edge of the switching output. Embodiments may also include an AND gate that is configured to threshold compare the rising edge to a configurable threshold to determine if a fault condition exists indicating clock drift between the first clock signal and the second clock signal and provide an indication of the fault condition based at least in part on the comparison.
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公开(公告)号：US11092464B2
公开(公告)日：2021-08-17
申请号：US16246918
申请日：2019-01-14
Applicant: Hamilton Sundstrand Corporation
Inventor： Gary L. Hess , Michael A. Wilson
Abstract: A system for determining an amplitude of a sinusoidal output waveform from a sensor includes a controller configured to provide a sample signal having a sample frequency that is four times a frequency of a sinusoidal excitation waveform provided to the sensor. The sensor has inductively-coupled primary and secondary windings that produce the sinusoidal output waveform from the secondary winding when the excitation waveform is provided to the primary winding. An analog-to-digital converter measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and the system calculates the amplitude based on the measurements of the first and second voltages.
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公开(公告)号：US20230195160A1
公开(公告)日：2023-06-22
申请号：US17553917
申请日：2021-12-17
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Gary L. Hess
CPC classification number: G06F1/08 , G06F1/12 , G06F9/30029 , G06F9/30021
Abstract: Provided are embodiments for monitoring clock drift. Embodiments may include an XOR gate that is configured to receive a first clock signal from a first clock source and a second clock signal from a second clock source, wherein the XOR logic gate is further configured to generate a switching output based on an XOR operation of the first clock signal and the second clock signal, and a rising edge detector and a falling edge detector that are configured to detect a rising edge and a falling edge of the switching output. Embodiments may also include an AND gate that is configured to threshold compare the rising edge to a configurable threshold to determine if a fault condition exists indicating clock drift between the first clock signal and the second clock signal and provide an indication of the fault condition based at least in part on the comparison.
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公开(公告)号：US10801863B2
公开(公告)日：2020-10-13
申请号：US16246956
申请日：2019-01-14
Applicant: Hamilton Sundstrand Corporation
Inventor： Gary L. Hess , Michael A. Wilson
IPC: G01D5/243
Abstract: A system for determining a phase angle of a sensor waveform relative to an excitation waveform includes a controller that provides an excitation signal having an excitation frequency and a sample signal having four times the excitation frequency. An exciter provides a sinusoidal excitation waveform at the excitation frequency to a primary winding, thereby inducing a sensor waveform in a secondary winding. An analog-to-digital converter (ADC) measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and a wrap-around ADC measures a first and second voltage of the sinusoidal excitation waveform. The first voltage measurements are made at the same time, and the second voltage measurements are made at the same time. The system calculates the phase angle based on the first voltage measurements and the second voltage measurements.
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公开(公告)号：US09960784B1
公开(公告)日：2018-05-01
申请号：US15487055
申请日：2017-04-13
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Harold J. Reyes
CPC classification number: H03M1/34 , H03K7/08 , H03M1/1245 , H03M1/485 , H03M1/504
Abstract: A sinusoidal-amplitude-to-digital-output circuit includes a comparator with an input terminal, a reference terminal and an output terminal. A digital bus is connected to the output terminal. A reference voltage source is connected to the reference terminal. A feedback resistor is connected in parallel with the comparator between the output terminal and the input terminal to provide hysteresis for noise rejection such that circuit converts voltage received at the input terminal into a digital pulse-width modulated waveform that varies non-linearly with amplitude of the voltage received at the input terminal.
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Patent Agency Ranking
公开(公告)号：US20250105655A1
公开(公告)日：2025-03-27
申请号：US18371807
申请日：2023-09-22
Applicant: Hamilton Sundstrand Corporation
Inventor： Steven A. Avritch , Michael A. Wilson , Alexander Trotman
Abstract: A capacitive system includes a module circuit card assembly including a first modular keying and alignment mechanism and a second modular keying and alignment mechanism. The first and second modular keying and alignment mechanisms are configured for mechanical alignment and electrical connection with a backplane circuit card assembly (CCA). A capacitor is mounted to the module circuit card assembly and is electrically connected to each of the first and second modular keying and alignment mechanisms through a charge/discharge circuit. The circuit is configured to: charge the capacitor with the module circuit card assembly connected to the backplane CCA, discharge the capacitor with the module circuit card assembly connected to the backplane CCA for providing backup power, and discharge the capacitor through a bleed resistor of the circuit upon disconnection of the module circuit card assembly from the backplane CCA.
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公开(公告)号：US11300986B2
公开(公告)日：2022-04-12
申请号：US17175583
申请日：2021-02-12
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Steven A. Avritch , Gary L. Hess
Abstract: A system comprises a first current balancer and a second current balancer. Each of the first and second current balancers includes a first input line for a first voltage source connected to a first output, a second input line for a second voltage source connected to a second output and is in parallel with the first input line, a first series pass element connected in series with the first input line, and a second series pass element connected in series with the second input line. The system further includes a controller operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.
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公开(公告)号：US20210190840A1
公开(公告)日：2021-06-24
申请号：US16722257
申请日：2019-12-20
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Gary L. Hess
Abstract: Systems, methods, and computer program products for sinusoidal nulling are provided. Aspects include transmitting, by a controller, an excitation signal to a first sensor, determining, by the controller, a target harmonic based at least on one or more characteristics of the excitation signal, receiving a return signal from the first sensor, sampling the return signal at a first sample rate based on the target harmonic, and adjusting a phase of the sampled return signal to null the target harmonic amplitude to form an adjusted return signal.
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公开(公告)号：US20190028099A1
公开(公告)日：2019-01-24
申请号：US15654430
申请日：2017-07-19
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Eduardo Ahuactzin Parra
IPC: H03K17/732
Abstract: A fast shut-off solenoid circuit network includes a solenoid circuit and a current dissipation circuit. The solenoid circuit is operable in response to an electrical current, and configured to operate in an enable mode and a disable mode. The current dissipation circuit is configured to dissipate the current discharged from the solenoid circuit in response to invoking the disable mode. The fast shut-off solenoid circuit network further includes a dissipation bypass circuit. The dissipation bypass circuit is configured to divert the current discharged by the solenoid circuit away from current dissipation circuit when operating in the enable mode.
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公开(公告)号：US20190027290A1
公开(公告)日：2019-01-24
申请号：US15654377
申请日：2017-07-19
Applicant: Hamilton Sundstrand Corporation
Inventor： Michael A. Wilson , Eduardo Ahuactzin Parra
IPC: H01F7/06
Abstract: A solenoid electrical diagnostic system includes a solenoid circuit operable in response to an electrical current. A low-side switch includes a low-side input configured to receive a pulsed voltage signal and a low-side output in signal communication with the solenoid circuit. The low-side switch continuously switches between an on-state and an off-state based on the pulsed voltage signal to adjust a level of the current flowing through the solenoid circuit. A solenoid monitoring unit generates a low-side output state signal based on an output voltage at the low-side output, and a low-side input state signal based on an input voltage at the low-side input. The solenoid electrical diagnostic system further includes an electronic hardware controller determines at least one operating condition of the solenoid circuit based on a comparison between the state signals and a threshold value.
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