公开(公告)号：US20200004648A1

公开(公告)日：2020-01-02

申请号：US16022990

申请日：2018-06-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Cong Xu ,  Naveen Muralimanohar ,  Harumi Kuno

IPC: G06F11/20 ,  G06F11/14 ,  G06F11/07 ,  G06F11/00 ,  G06F11/36 ,  G06F15/18 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F9/455

Abstract: While scheduled checkpoints are being taken of a cluster of active compute nodes distributively executing an application in parallel, a likelihood of failure of the active compute nodes is periodically and independently predicted. Responsive to the likelihood of failure of a given active compute node exceeding a threshold, the given active compute node is proactively migrated to a spare compute node of the cluster at a next scheduled checkpoint. Another spare compute node of the cluster can perform prediction and migration. Prediction can be based on both hardware events and software events regarding the active compute nodes.

公开(公告)号：US11556438B2

公开(公告)日：2023-01-17

申请号：US16994784

申请日：2020-08-17

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Cong Xu ,  Naveen Muralimanohar ,  Harumi Kuno

IPC: G06F11/20 ,  G06F11/14 ,  G06F11/07 ,  G06F11/00 ,  G06F11/36 ,  G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F9/455 ,  G06N20/00

Abstract: While scheduled checkpoints are being taken of a cluster of active compute nodes distributively executing an application in parallel, a likelihood of failure of the active compute nodes is periodically and independently predicted. Responsive to the likelihood of failure of a given active compute node exceeding a threshold, the given active compute node is proactively migrated to a spare compute node of the cluster at a next scheduled checkpoint. Another spare compute node of the cluster can perform prediction and migration. Prediction can be based on both hardware events and software events regarding the active compute nodes.

公开(公告)号：US10769017B2

公开(公告)日：2020-09-08

申请号：US15960302

申请日：2018-04-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Cong Xu ,  Itir Akgun ,  Paolo Faraboschi

IPC: G06F11/00 ,  G06F11/14 ,  H04L29/08

Abstract: In some examples, with respect to adaptive multi-level checkpointing, a transfer parameter associated with transfer of checkpoint data from a node-local storage to a parallel file system may be ascertained for the checkpoint data stored in the node-local storage. The transfer parameter may be compared to a specified transfer parameter threshold. A determination may be made, based on the comparison of the transfer parameter to the specified transfer parameter threshold, as to whether to transfer the checkpoint data from the node-local storage to the parallel file system.

公开(公告)号：US10725940B2

公开(公告)日：2020-07-28

申请号：US16167494

申请日：2018-10-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi ,  Cong Xu ,  Ping Chi ,  Sai Rahul Chalamalasetti ,  Andrew C. Walton

IPC: G06F13/16 ,  G06F15/76 ,  G06F9/38

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

公开(公告)号：US10324644B2

公开(公告)日：2019-06-18

申请号：US15476185

申请日：2017-03-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kaisheng Ma ,  Qiong Cai ,  Cong Xu ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F3/06 ,  G06F15/78 ,  G06F9/48 ,  G06F9/50

Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.

公开(公告)号：US20190056872A1

公开(公告)日：2019-02-21

申请号：US16167494

申请日：2018-10-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi ,  Cong Xu ,  Ping Ping ,  Sai Rahul Chalamalasetti ,  Andrew C. Walton

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/38

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

公开(公告)号：US10175906B2

公开(公告)日：2019-01-08

申请号：US15325118

申请日：2014-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Erik Ordentlich ,  Cong Xu

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G11C13/00

Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

公开(公告)号：US10108351B2

公开(公告)日：2018-10-23

申请号：US15190276

申请日：2016-06-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi ,  Cong Xu ,  Ping Chi ,  Sai Rahul Chalamalasetti ,  Andrew C. Walton

IPC: G06F3/06

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

公开(公告)号：US20170192711A1

公开(公告)日：2017-07-06

申请号：US15325118

申请日：2014-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Erik Ordentlich ,  Cong Xu

IPC: G06F3/06

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0679 ,  G11C7/1012 ,  G11C13/0069 ,  G11C2213/77

Abstract: In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

公开(公告)号：US20190340510A1

公开(公告)日：2019-11-07

申请号：US15967835

申请日：2018-05-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sicheng Li ,  Cong Xu ,  Tsung Ching Huang

IPC: G06N3/08 ,  G06N3/04

Abstract: A technique includes modifying a neural network model to sparsify the model. The model includes a plurality of kernel element weights, which are parameterized according to a plurality of dimensions. Modifying the model includes, in a given iteration of the plurality of iterations, training the model based on a structure regularization in which kernel element weights that share a dimension in common are removed as a group to create corresponding zero kernel elements in the model; and compressing the model to exclude zero kernel element weights from the model to prepare the model to be trained in another iteration.