摘要:
An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.
摘要:
A test device and method is disclosed. In one embodiment, the test device includes a precision signal generator for generating a test signal, which generator is connected via a respective connecting line to a respective input contact intended for connection to an input of an integrated circuit, and at least one reference signal generator for generating a reference signal. Furthermore, at least one comparator unit is provided for a respective input contact said comparator unit being able to be operated in a test mode. In the test mode, the test signal is compared with the reference signal. The precision signal generator is turned off by the comparator unit if the test signal exceeds or falls below the reference signal.
摘要:
M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0≦n ≦N−1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tφ is calculated by ∑ i = 0 M - 1 Idx ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.
摘要翻译:接收测试信号和参考信号的M个周期。 在每种情况下,测试信号和参考信号的周期都是长的。 测试信号以采样频率f N 1 = 1 / T S N的采样值采样。 此外,N * T S = M * T S,其中N> M。 采样值逐渐被n编号,0 <= n <= N-1。 采样值相对于参考信号具有限定的相对相移。 相位偏移T SUB>由
摘要:
The electrical test circuit (5) comprises a first input (51) for receiving a test signal of an integrated circuit (4), a second input (52) for receiving a control signal and a third input (53) for receiving a normalized reference signal, particularly one that is formed to be synchronous with the test signal. Using a control device (55) of the electrical test circuit (5), the deviation and/or the amplitude and/or the phase of the reference signal and/or of the test signal can be varied. A measuring device (56) generates, by subtracting the reference signal from the test signal, a difference signal which is output via an output (54).
摘要:
M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0≦n ≦N−1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tφ is calculated by ∑ i = 0 M - 1 Idx ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.
摘要:
An electrical test circuit is disclosed. In one embodiment, the electrical test circuit includes a first input for receiving a test signal of an integrated circuit, a second input for receiving a control signal and a third input for receiving a normalized reference signal, particularly one that is formed to be synchronous with the test signal. Using a control device of the electrical test circuit, the deviation and/or the amplitude and/or the phase of the reference signal and/or of the test signal can be varied. A measuring device generates, by subtracting the reference signal from the test signal, a difference signal which is output via an output.
摘要:
The electronic test circuit for an integrated circuit to be tested has an input for receiving an analog data stream (23), a programmable digital line emulator (TPE1) for emulating properties of a transmission path and an output for emitting an analog data stream (24) having a signal-to-noise ratio which can be adjusted using the programmable digital line emulator (TPE1).
摘要:
An electrical circuit including a test circuit and a method of testing electrical circuits is disclosed. In one embodiment, the circuit includes a electrical short-circuit protective circuit according to the invention for protecting an input contact against short-circuit having an input which is intended for connection to a signal generator, and an output which is intended for connection to a input contact. The input contact can be decoupled from the region lying upstream of the input of the electrical short-circuit protective circuit by the electrical short-circuit protective circuit.
摘要:
The electronic test circuit for an integrated circuit to be tested has an input for receiving an analog data stream (23), a programmable digital line emulator (TPE1) for emulating properties of a transmission path and an output for emitting an analog data stream (24) having a signal-to-noise ratio which can be adjusted using the programmable digital line emulator (TPE1).
摘要:
A test device contains a data pattern generator for providing a delta-sigma-modulated data stream sampled with a sampling frequency fs at its output. A phase modulator generates a test clock subjected to jitter and having the clock frequency f1 at its output. The output of the data pattern generator is connected to a terminal for connection to a data input of a semiconductor component to be tested. The output of the phase modulator is connected to a terminal for connection to a clock input of a semiconductor component to be tested. An evaluation device determines the jitter parameters of the input sinusal at the input of the data device from the low-frequency component of the input sinusal. In this case, the low-frequency component contains only frequency components of frequencies which are less than half the sampling frequency fs/2.