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    SELF-ADJUSTABLE END-TO-END STACK PROGRAMMING
    11.
    发明申请
    SELF-ADJUSTABLE END-TO-END STACK PROGRAMMING 有权

    公开(公告)号：US20210263713A1

    公开(公告)日：2021-08-26

    申请号：US16799637

    申请日：2020-02-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Dejan S. Milojicic ,  Mehmet Kivanc Ozonat ,  Sergey Serebryakov

    IPC: G06F8/35 ,  G06F9/445

    Abstract: Systems and methods are provided for optimizing parameters of a system across an entire stack, including algorithms layer, toolchain layer, execution or runtime layer, and hardware layer. Results from the layer-specific optimization functions of each domain can be consolidated using one or more consolidation optimization functions to consolidate the layer-specific optimization results, capturing the relationship between the different layers of the stack. Continuous monitoring of the programming model during execution may be implemented and can enable the programming model to self-adjust based on real-time performance metrics. In this way, programmers and system administrators are relieved of the need for domain knowledge and are offered a systematic way for continuous optimization (rather than an ad hoc approach).

    Tunable and dynamically adjustable error correction for memristor crossbars
    12.
    发明授权
    Tunable and dynamically adjustable error correction for memristor crossbars 有权

    公开(公告)号：US10452472B1

    公开(公告)日：2019-10-22

    申请号：US15997030

    申请日：2018-06-04

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Catherine Graves ,  John Paul Strachan ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

    IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09 ,  H03M13/35

    Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.

    CAMS FOR LOW LATENCY COMPLEX DISTRIBUTION SAMPLING
    13.
    发明公开
    CAMS FOR LOW LATENCY COMPLEX DISTRIBUTION SAMPLING 审中-公开

    公开(公告)号：US20240153555A1

    公开(公告)日：2024-05-09

    申请号：US18411222

    申请日：2024-01-12

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Catherine Graves ,  Giacomo Pedretti ,  Sergey Serebryakov ,  John Paul Strachan

    IPC: G11C13/00 ,  G06N7/01 ,  G11C15/04

    CPC classification number: G11C13/004 ,  G06N7/01 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C15/04

    Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.

    Resiliency for machine learning workloads
    14.
    发明授权
    Resiliency for machine learning workloads 有权

    公开(公告)号：US11868855B2

    公开(公告)日：2024-01-09

    申请号：US16673868

    申请日：2019-11-04

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sai Rahul Chalamalasetti ,  Sergey Serebryakov ,  Dejan S. Milojicic

    IPC: G06N20/00 ,  G06F16/901 ,  G06F21/60

    CPC classification number: G06N20/00 ,  G06F16/901 ,  G06F21/602

    Abstract: In exemplary aspects, a golden data structure can be used to validate the stability of machine learning (ML) models and weights. The golden data structure includes golden input data and corresponding golden output data. The golden output data represents the known correct results that should be output by a ML model when it is run with the golden input data as inputs. The golden data structure can be stored in a secure memory and retrieved for validation separately or together with the deployment of the ML model for a requested ML operation. If the golden data structure is used to validate the model and/or weights concurrently with the performance of the requested operation, the golden input data is combined with the input data for the requested operation and run through the model. Relevant outputs are compared with the golden output data to validate the stability of the model and weights.

    Anomalous behavior detection by an artificial intelligence-enabled system with multiple correlated sensors
    16.
    发明授权
    Anomalous behavior detection by an artificial intelligence-enabled system with multiple correlated sensors 有权

    公开(公告)号：US11774956B2

    公开(公告)日：2023-10-03

    申请号：US17207540

    申请日：2021-03-19

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sergey Serebryakov ,  Tahir Cader ,  Deepak Nanjundaiah

    IPC: G05B23/02 ,  G06N20/00

    CPC classification number: G05B23/0235 ,  G05B23/024 ,  G05B23/0262 ,  G05B23/0297 ,  G06N20/00

    Abstract: Multi-metric artificial intelligence (AI)/machine learning (ML) models for detection of anomalous behavior of a machine/system are disclosed. The multi-metric AI/ML models are configured to detect anomalous behavior of systems having multiple sensors that measure correlated sensor metrics such as coolant distribution units (CDUs). The multi-metric AI/ML models perform the anomalous system behavior detection in a manner that enables both a reduction in the amount of sensor instrumentation needed to monitor the system's operational behavior as well as a corresponding reduction in the complexity of the firmware that controls the sensor instrumentation. As such, AI-enabled systems and corresponding methods for anomalous behavior detection disclosed herein offer a technical solution to the technical problem of increased failure rates of existing multi-sensor systems, which is caused by the presence of redundant sensor instrumentation that necessitates complex firmware for controlling the sensor instrumentation.

    Adjustable precision for multi-stage compute processes
    18.
    发明授权
    Adjustable precision for multi-stage compute processes 有权

    公开(公告)号：US11385863B2

    公开(公告)日：2022-07-12

    申请号：US16052218

    申请日：2018-08-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  Sergey Serebryakov ,  John Paul Strachan

    IPC: G06F7/483 ,  G06N3/08 ,  G06N3/063

    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.

    RESILIENCY FOR MACHINE LEARNING WORKLOADS
    19.
    发明申请
    RESILIENCY FOR MACHINE LEARNING WORKLOADS 有权

    公开(公告)号：US20210133624A1

    公开(公告)日：2021-05-06

    申请号：US16673868

    申请日：2019-11-04

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sai Rahul Chalamalasetti ,  Sergey Serebryakov ,  Dejan S. Milojicic

    IPC: G06N20/00 ,  G06F21/60 ,  G06F16/901

    Abstract: In exemplary aspects, a golden data structure can be used to validate the stability of machine learning (ML) models and weights. The golden data structure includes golden input data and corresponding golden output data. The golden output data represents the known correct results that should be output by a ML model when it is run with the golden input data as inputs. The golden data structure can be stored in a secure memory and retrieved for validation separately or together with the deployment of the ML model for a requested ML operation. If the golden data structure is used to validate the model and/or weights concurrently with the performance of the requested operation, the golden input data is combined with the input data for the requested operation and run through the model. Relevant outputs are compared with the golden output data to validate the stability of the model and weights.

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