公开(公告)号：US20090010063A1

公开(公告)日：2009-01-08

申请号：US11773771

申请日：2007-07-05

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.

Abstract translation: NAND型闪存包括第一至第三存储单元晶体管，其具有串联连接在第一和第二选择晶体管中的每一个的电流路径的一端之间的电流路径，并且每个存储单元晶体管具有控制栅极和电荷存储层，第一和第二 存储单元晶体管与第一和第二选择晶体管相邻，第三存储单元晶体管位于第一和第二存储单元晶体管之间，第三存储单元晶体管保持具有不少于3位的数据，第一存储单元晶体管保持2 通过跳过下页来写入中间页和上页的位数数据，以及写入中间页时设置的下页验证电压，并且在写入上页时设置中间页验证电压，改变位置 第一存储单元晶体管的阈值分布。

公开(公告)号：US20080239805A1

公开(公告)日：2008-10-02

申请号：US11863915

申请日：2007-09-28

Applicant: Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

Inventor： Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5646

Abstract: A nonvolatile semiconductor memory according to the present invention includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when performing 4-value data programming, read or erasure with respect to at least one of the plurality of memory cells, selecting and applying a voltage to a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines; wherein the data reading and programming control section includes an adjacent memory cell data reading section for reading, at a reading voltage of a predetermined reading voltage level, whether or not data is programmed in a lower page of a second memory cell adjacent to a first memory cell in the memory cell array, and generating adjacent memory cell state data which represents a data state of the second memory cell; an adjacent memory cell data memory section for storing the adjacent memory cell state data generated by the adjacent memory cell data reading section; a reading voltage level control section for defining a plurality of predetermined reading voltage verify levels for reading data from the first memory cell based on the adjacent memory cell state data; a data reading section for reading the data from the first memory cell at a plurality of reading voltages corresponding to the plurality of predetermined reading voltage verify levels; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.

Abstract translation: 根据本发明的非易失性半导体存储器包括：包括多个电可写存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 以及数据读取和编程控制部分，用于当对所述多个存储器单元中的至少一个进行4值数据编程时，读取或擦除所述多个存储器单元中的至少一个，选择并施加电压到相应的字线和相应的位线之间 所述多个字线和所述多个位线; 其中所述数据读取和编程控制部分包括相邻存储单元数据读取部分，用于在预定读取电压电平的读取电压下读取与第一存储器相邻的第二存储器单元的下部页面中的数据是否被编程 并且生成表示第二存储单元的数据状态的相邻存储单元状态数据; 相邻的存储单元数据存储部，用于存储由相邻存储单元数据读取部生成的相邻的存储单元状态数据; 读取电压电平控制部分，用于基于相邻的存储器单元状态数据定义用于从第一存储器单元读取数据的多个预定读取电压验证电平; 数据读取部分，用于以对应于多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据确定在第一存储器单元中哪个数据被编程。

公开(公告)号：US20110205801A1

公开(公告)日：2011-08-25

申请号：US13016286

申请日：2011-01-28

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: In writing operation, charge pumps of a memory apply any of first to n-th voltages which are different from each other. An application-voltage selector selects voltages to be applied to WLs among the first to n-th voltages. A word-line number register stores the number of WLs to which each of the first to n-th voltages is to be applied for the first to n-th voltages. A storage stores a correspondence table that stores a relationship between the number of WLs for each of the first to n-th voltages and the number of charge pumps allocated to the first to n-th voltages. A generation-voltage selector allocates charge pumps to generate the first to n-th voltages based on the correspondence table according to the number of WLs for each of the first to n-th voltages. Each charge pump generates any of the first to n-th voltages allocated by the generation-voltage selector.

Abstract translation: 在写入操作时，存储器的电荷泵应用彼此不同的第一至第n电压中的任何一个。 应用电压选择器选择在第一至第n电压中施加到WL的电压。 字线号寄存器存储要施加第一至第n电压的第一至第n电压中的每一个的WL的数量。 存储器存储存储第一至第n电压中的每一个的WL的数量与分配给第一至第n电压的电荷泵的数量之间的关系的对应表。 发电电压选择器基于根据第一至第n电压中的每一个的WL的数量的对应表，分配电荷泵以产生第一至第n电压。 每个电荷泵产生由发电电压选择器分配的第一至第n电压中的任一个。

公开(公告)号：US20100124110A1

公开(公告)日：2010-05-20

申请号：US12564425

申请日：2009-09-22

Applicant: Hitoshi SHIGA ,  Yoshihisa KONDO

Inventor： Hitoshi SHIGA ,  Yoshihisa KONDO

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/00

Abstract: A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.

Abstract translation: 半导体存储装置包括：读出放大器电路; 第一数据保持电路和第二数据保持电路，被配置为保持数据和阈值电压信息，第二数据保持电路将数据和阈值电压信息输出到外部; 以及控制电路，被配置为控制操作。 感测放大器电路被配置为同时执行数据读取操作和阈值电压信息读取操作。 控制电路被配置为控制读取操作，使得先前完成读取操作的数据或阈值电压信息中的任何一个从第二数据保持电路输出，另一个数据或阈值电压信息 读取操作尚未完成，从存储单元阵列中读出并保留在第一数据保持电路中。

公开(公告)号：US20080082735A1

公开(公告)日：2008-04-03

申请号：US11864074

申请日：2007-09-28

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G06F13/00

CPC classification number: G06F13/28

Abstract: A nonvolatile semiconductor device includes a first flash memory device; a second flash memory device in which data programming and/or reading is faster than in said first flash memory device; an address conversion table which correlates a logical address of a memory cell to a physical address designating said memory cell of said first and/or said second flash memory; an interface part which accepts an access request to a memory cell, an address conversion table search part which searches a physical address an access part which accesses a memory cell a counting part which counts the number of times a physical address has been accessed and generates an access count value of said physical address; a comparison part which compares whether said access count value of said physical address is more than a threshold or not and a transmitting part which transmits data to said second flash memory device.

Abstract translation: 非易失性半导体器件包括第一闪存器件; 第二闪速存储器件，其中数据编程和/或读取比在所述第一闪存器件中快; 地址转换表，其将存储器单元的逻辑地址与指定所述第一和/或所述第二闪存的所述存储单元的物理地址相关联; 接收对存储单元的访问请求的接口部分，地址转换表搜索部，其对物理地址进行访问存储单元的访问部，对计数物理地址被访问次数进行计数的计数部， 所述物理地址的访问计数值; 比较所述物理地址的所述访问计数值是否大于阈值的比较部分，以及向所述第二快闪存储器件发送数据的发送部。

公开(公告)号：US20080073673A1

公开(公告)日：2008-03-27

申请号：US11858556

申请日：2007-09-20

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: H01L27/105 ,  G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a peripheral circuit is designed. A M0 wire of a first wiring layer which is formed on a semiconductor substrate is used as a wire used within a macro cell. The basic cell and the macro cell are connected by a M1 wire of a second wiring layer which is formed on the first wiring layer and a M2 wire M2 of a third wiring layer. The transistor layout of basic cells and macro cells is designed and verified in advance and stored in a cell library, and auto routing by a standard method may be carried out.

Abstract translation: 使几种基本单元的高度H相同，并且准备长度为该基本单元的高度H的整数倍的几种宏单元，将基本单元和宏单元混合，并且 设计外围电路的电路。 使用形成在半导体基板上的第一布线层的M0线作为在宏电池内使用的导线。 基本单元和宏单元通过形成在第一布线层上的第二布线层的M1线和第三布线层的M2线M2连接。 基本单元和宏单元的晶体管布局预先设计和验证并存储在单元库中，并且可以执行通过标准方法的自动布线。

公开(公告)号：US20080013371A1

公开(公告)日：2008-01-17

申请号：US11769383

申请日：2007-06-27

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/02

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/88 ,  G11C2211/5621 ,  G11C2211/5646

Abstract: A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines. A word-line control circuit controls a word-line voltage applied to a word-line. A control circuit controls the word-line control circuit and the bit-line control circuit. The control circuit performs a mode in which, to distinguish a fault block, all or specific memory cells in a fault block may be written so that all or specific memory cells in the fault block have a threshold voltage higher than a word-line voltage applied to a selected word-line when reading a first page data of the sets of page data.

Abstract translation: 存储单元阵列包括能够存储多值数据的多个存储单元。 位线控制电路包括连接到位线的数据存储电路，并且每个存储包括在多值数据中的多组页数据中的一个，位线控制电路控制施加到位的位线电压 线。 字线控制电路控制施加到字线的字线电压。 控制电路控制字线控制电路和位线控制电路。 控制电路执行这样的模式，为了区分故障块，可以写入故障块中的全部或特定存储单元，使得故障块中的全部或特定存储单元的阈值电压高于施加的字线电压 当读取页面数据集合的第一页数据时，到所选择的字线。