公开(公告)号：US20100208519A1

公开(公告)日：2010-08-19

申请号：US12706306

申请日：2010-02-16

Applicant: Hitoshi SHIGA ,  Osamu Nagao

Inventor： Hitoshi SHIGA ,  Osamu Nagao

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/3404

Abstract: First and second data retaining circuits retain data read from memory cell and threshold voltage information indicating where in one of plural threshold voltage distributions threshold voltage of memory cell is located. Calculation device executes calculations among data retained in first and second data retaining circuit and data read by sense amplifier.Control circuit executes first operation of reading data from adjoining memory cell connected to second word line adjoining first word line connected to selected memory cell and retaining the data in first data retaining circuit, and second operation of changing respective word line voltages applied to first word line for reading data or threshold voltage information among plural values and selecting one of plural data read out by the plural values based on data retained in first data retaining circuit. Third operation of externally outputting selected data is executed simultaneously with one of successive first and second operations.

Abstract translation: 第一和第二数据保持电路保持从存储单元读取的数据和指示存储单元的多个阈值电压分布阈值电压位于何处的阈值电压信息。 计算装置执行在第一和第二数据保持电路中保留的数据和由读出放大器读取的数据之间的计算。 控制电路执行从连接到与选择的存储单元连接的第一字线相邻的第二字线的相邻存储单元读取数据并将数据保存在第一数据保持电路中的第一操作，以及改变施加到第一字线的各字线电压的第二操作 用于在多个值之间读取数据或阈值电压信息，并且基于保留在第一数据保持电路中的数据选择由多个值读出的多个数据中的一个。 在连续的第一和第二操作之一中同时执行外部输出所选数据的第三操作。

公开(公告)号：US20080074929A1

公开(公告)日：2008-03-27

申请号：US11838605

申请日：2007-08-14

Applicant: Hitoshi SHIGA ,  Kiyofumi Sakurai ,  Kenji Mima

Inventor： Hitoshi SHIGA ,  Kiyofumi Sakurai ,  Kenji Mima

IPC: G11C11/34 ,  G06F17/50 ,  H01L23/52

CPC classification number: G06F17/5077 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/11898

Abstract: An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

Abstract translation: ASIC包括沿第一方向延伸的第一线和与第一线并联延伸的第二线，并且两者均放置在第一线层上; 以及放置在所述第一线层上方的二线层上并且在所述线的上方延伸并且在与所述第一方向相交并穿过第一通孔的第二方向上方的所述第二线上的第三线是 连接到第一线，以及与第三线分离的第四线，该第三线在第一线上方平行并且在第二线上方延伸，以及与第三线和第四线分离的第五线， 并且在最小的空间中沿平行方向延伸并穿过第二通孔的第二线连接到第二线，其中，第五线的一端延伸到第二线和第一线之间的中心， 电线从二线以上。

公开(公告)号：US20070097750A1

公开(公告)日：2007-05-03

申请号：US11564887

申请日：2006-11-30

Applicant: Hitoshi SHIGA ,  Chih-Hung Wang ,  Chin Lin

Inventor： Hitoshi SHIGA ,  Chih-Hung Wang ,  Chin Lin

IPC: G11C11/34

CPC classification number: G11C16/344 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/16 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.

Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。

公开(公告)号：US20120063234A1

公开(公告)日：2012-03-15

申请号：US13226180

申请日：2011-09-06

Applicant: Hitoshi SHIGA ,  Masahiro Yoshihara

Inventor： Hitoshi SHIGA ,  Masahiro Yoshihara

IPC: G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.

Abstract translation: 根据一个实施例，存储器系统包括第一非易失性半导体存储器，第二非易失性半导体存储器和控制器。 第一存储器具有存储器单元并且执行与存储器单元相关的写入，读取和擦除操作中的至少一个的第一操作。 第一操作包括消耗等于或高于预定电流的电流的第一子操作和第二子操作。 第二存储器具有存储单元并且执行与存储单元相关的写入，读取和擦除操作中的至少一个的第二操作。 第二操作包括消耗等于或高于预定电流的电流的第三子操作和第四子操作。 控制器控制第一存储器和第二存储器的第一操作和第二操作。

公开(公告)号：US20110228615A1

公开(公告)日：2011-09-22

申请号：US13033259

申请日：2011-02-23

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C29/846

Abstract: According to one embodiment, a semiconductor memory device includes unit structures. Each unit structure includes bit lines, memory cells, sense amplifiers, a first data line, a computing circuit, a second data line, and data latches. The bit lines are connected to memory cells. The sense amplifiers are connected to respective bit lines adjacent to each other. The first data line is commonly connected to the sense amplifiers. The computing circuit is connected to the first data line. The second data line is connected to the computing circuit. The data latches are connected to the second data line. The unit structures are independent from one another. At least one of the unit structures is a spare unit structure. One of the unit structures is configured to be replaceable with the spare unit structure.

Abstract translation: 根据一个实施例，半导体存储器件包括单元结构。 每个单元结构包括位线，存储单元，读出放大器，第一数据线，计算电路，第二数据线和数据锁存器。 位线连接到存储单元。 读出放大器连接到彼此相邻的相应位线。 第一条数据线通常连接到读出放大器。 计算电路连接到第一数据线。 第二数据线连接到计算电路。 数据锁存器连接到第二条数据线。 单位结构彼此独立。 至少一个单元结构是备用单元结构。 其中一个单元结构被配置为可替换备用单元结构。

公开(公告)号：US20100080056A1

公开(公告)日：2010-04-01

申请号：US12557898

申请日：2009-09-11

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04 ,  G11C16/06 ,  H01L29/788

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5641 ,  H01L27/11521

Abstract: A semiconductor memory system includes: a memory cell array having a plurality of memory cells arranged therein, the plurality of memory cells capable of storing N bits of information in each memory cell (where N is a natural number more than 3, other than a power of two); a control circuit configured to control read, write, and erase operations on the memory cell array; and an ECC circuit configured to correct data read from the memory cell array, based on redundant data. The memory cells that share one of word lines and can be written or read at a time are configured to store multiple pages of data therein. A total amount of data stored in the multiple pages is set to a power-of-two number of bits, and the redundant data is stored in a residual portion of the multiple pages.

Abstract translation: 半导体存储器系统包括：存储单元阵列，其中布置有多个存储器单元，所述多个存储单元能够在每个存储单元中存储N位信息（其中N是大于3的自然数，除了功率 的两个）; 控制电路，被配置为控制对所述存储单元阵列的读，写和擦除操作; 以及ECC电路，被配置为基于冗余数据校正从存储单元阵列读取的数据。 共享字线之一并且可以一次写入或读取的存储单元被配置为在其中存储多页数据。 存储在多页中的数据的总量被设置为两位数，并且冗余数据被存储在多页的剩余部分中。

公开(公告)号：US20090154244A1

公开(公告)日：2009-06-18

申请号：US12333656

申请日：2008-12-12

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04 ,  G11C16/06 ,  G11C8/00

CPC classification number: G11C8/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line for programming data; a word line selection circuit which selects a word line among the plurality of word lines which is connected to a memory cell to be programmed with data; a voltage application circuit which applies a programming voltage to the selected word line according to the parameter; a verify circuit which performs verification of programmed data; a control part which outputs a signal for selecting a word line and repeats the operations of the voltage application circuit until the verification is successful; a calculation circuit which calculates an average value of the number of times the control part repeats the operations of the voltage application circuit per each word line; and a parameter setting circuit which sets the parameter using the average value calculated.

Abstract translation: 根据本发明的一个实施例的非易失性半导体存储器件包括：包括多个字线的存储单元阵列; 参数存储部，其存储与应用于用于编程数据的字线的编程电压相关的参数; 字线选择电路，其选择连接到要被数据编程的存储单元的多个字线中的字线; 电压施加电路，其根据所述参数对所选择的字线施加编程电压; 执行编程数据验证的验证电路; 控制部，其输出用于选择字线的信号，并重复所述电压施加电路的动作，直到所述验证成功为止; 计算电路，其计算控制部分重复每个字线的电压施加电路的操作次数的平均值; 以及使用所计算的平均值来设定参数的参数设定电路。

公开(公告)号：US20120051134A1

公开(公告)日：2012-03-01

申请号：US13217512

申请日：2011-08-25

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04

CPC classification number: G11C29/025 ,  G11C16/26 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: When performing a word line leak test to determine a leak state of the word lines, the control circuit applies, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data. Thereafter, it switches the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state. After a lapse of a certain time from switching of the transfer transistors to a nonconductive state, it activates the sense amplifier circuit to perform a read operation in the memory cell array. Then it compares a result of the read operation with an expectation value corresponding to the test pattern data.

Abstract translation: 当进行字线泄漏测试以确定字线的泄漏状态时，控制电路从电压控制电路向连接到用测试图形数据写入的存储单元阵列的字线施加与测试图案数据相对应的电压 。 此后，它将转移晶体管切换到非导通状态，从而将字线设置为浮置状态。 在从转换晶体管切换到非导通状态经过一段时间之后，它激活读出放大器电路，以在存储单元阵列中执行读取操作。 然后将读取操作的结果与对应于测试图案数据的期望值进行比较。

公开(公告)号：US20110044106A1

公开(公告)日：2011-02-24

申请号：US12916856

申请日：2010-11-01

Applicant: Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

Inventor： Hitoshi SHIGA ,  Susumu Fujimura ,  Yoshihiko Shindo

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5646

Abstract: A nonvolatile semiconductor memory that includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section. The data reading and programming control section includes: an adjacent memory cell data reading section; an adjacent memory cell data memory section; a reading voltage level control section; a data reading section for reading the data from a first memory cell at a plurality of reading voltages corresponding to a plurality of predetermined reading voltage verify levels controlled using the reading voltage level control section; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section.

Abstract translation: 一种非易失性半导体存储器，包括：包括多个电可写入存储单元的存储单元阵列; 连接到所述多个存储单元的多个字线和多个位线; 和数据读取和编程控制部分。 数据读取和编程控制部分包括：相邻存储单元数据读取部分; 相邻存储单元数据存储器部分; 读取电压电平控制部; 数据读取部分，用于以对应于使用读取电压电平控制部分控制的多个预定读取电压验证电平的多个读取电压读取来自第一存储器单元的数据; 以及数据确定部分，用于基于由数据读取部分读取的数据确定在第一存储器单元中哪个数据被编程。

公开(公告)号：US20110044103A1

公开(公告)日：2011-02-24

申请号：US12838811

申请日：2010-07-19

Applicant: Hitoshi SHIGA

Inventor： Hitoshi SHIGA

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/3436

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner; a data bus configured to transmit write data to be written to the plurality of memory cells, the write data being configured by a plurality of unit data; a column selection unit configured by a plurality of data latches, each of the data latches being configured to directly receive the unit data inputted from the data bus and to retain the unit data; and a control unit configured to control activation/non-activation of the data latches. During a programming operation, for each unit data inputted to the column selection unit, the control unit activates one of the data latches corresponding to a certain one of the memory cells where the unit data is to be stored.

Abstract translation: 非易失性半导体存储器件包括：由多个第一和第二线路以及多个存储器单元配置的存储器单元阵列，每个存储单元由第一和第二线路选择，并被配置为存储多位数据 非挥发性; 数据总线，被配置为发送要写入到所述多个存储器单元的写入数据，所述写入数据由多个单位数据配置; 由多个数据锁存器配置的列选择单元，每个数据锁存器被配置为直接接收从数据总线输入的单元数据并保持单元数据; 以及控制单元，被配置为控制数据锁存器的激活/非激活。 在编程操作期间，对于输入到列选择单元的每个单元数据，控制单元激活对应于要存储单元数据的存储单元中的某一个存储单元的数据锁存器之一。