公开(公告)号：US20070155092A1

公开(公告)日：2007-07-05

申请号：US11319357

申请日：2005-12-29

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7881 ,  H01J9/025 ,  H01L27/0207 ,  H01L29/40114

摘要： A method for forming a tip is disclosed. A layer is formed overlying a substrate. A mask layer is formed overlying the layer. The mask is patterned to form a mask pattern comprising an inner portion and an outer portion, wherein the inner portion is surrounded by the outer portion. The layer uncovered by the mask pattern is treated to form a reaction mask, wherein at least one portion of the reaction mask connect to form a tip of the layer under the inner portion of the mask pattern.

摘要翻译： 公开了一种用于形成尖端的方法。 层叠在衬底上方。 形成覆盖层的掩模层。 将掩模图案化以形成包括内部部分和外部部分的掩模图案，其中内部部分被外部部分包围。 处理由掩模图案覆盖的层以形成反应掩模，其中反应掩模的至少一部分连接以在掩模图案的内部部分的下方形成该顶层。

公开(公告)号：US20080074922A1

公开(公告)日：2008-03-27

申请号：US11533791

申请日：2006-09-21

申请人： I-Ming Chang ,  Chia-Ta Hsieh ,  Hsiang-Tai Lu

发明人： I-Ming Chang ,  Chia-Ta Hsieh ,  Hsiang-Tai Lu

IPC分类号： G11C16/04

CPC分类号： G11C16/0441

摘要： A 2-transistor (2T) memory cell comprising a first transistor and a second transistor. The first and second transistors respectively have a source and a drain separated apart by a channel thereof, a floating gate over the channel near the source side, and a control gate over the floating gate and the channel near the drain side. The sources, floating gates, and control gates of the first and second transistors are respectively mutually connected. In addition, driving capability of the second transistor is substantially larger than that of the first transistor.

摘要翻译： 一种包括第一晶体管和第二晶体管的2-晶体管（2T）存储单元。 第一和第二晶体管分别具有通过其沟道分开的源极和漏极，在源极附近的沟道上方的浮动栅极以及在浮置栅极和靠近漏极侧的沟道的控制栅极。 第一和第二晶体管的源极，浮置栅极和控制栅极分别相互连接。 此外，第二晶体管的驱动能力明显大于第一晶体管的驱动能力。

公开(公告)号：US20060019444A1

公开(公告)日：2006-01-26

申请号：US10895881

申请日：2004-07-21

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US20050156223A1

公开(公告)日：2005-07-21

申请号：US10762166

申请日：2004-01-21

申请人： Hsiang-Tai Lu ,  Chia-Ta Hsieh

发明人： Hsiang-Tai Lu ,  Chia-Ta Hsieh

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A structure for flash memory cells with improved endurance characteristics is disclosed. Isolation regions are formed in a semiconductor region separating cells and also separating programming bit line channel regions of a cell from reading bit line channel regions of a cell. A conductive floating gates has a first portion in the programming bit line channel region of a cell and a second portion in the reading bit line channel region of the cell and a third connecting portion passing over an isolation region. A conductive control gate is separated from the floating gate by an intergate insulator layer and has a first portion entirely disposed over the first floating gate portion, where the first floating gate portion completely covers the space between a source region and a drain region, a second portion disposed over the second floating gate portion, where the second floating gate portion does not extend all the way from a source region to a drain region, the second control gate portion completing the covering of the space between a source region and a drain region and a third connecting portion disposed over the third floating gate portion. A programming bit line channel contact line and a reading bit line channel contact line are disposed over a covering insulator layer and connect to drain regions through the covering insulator layer.

摘要翻译： 公开了一种具有改善耐久特性的闪存单元的结构。 隔离区形成在分离单元的半导体区域中，并且还将单元的编程位线通道区域与单元的位线通道区域分开。 导电浮栅具有单元的编程位线沟道区中的第一部分和单元的读取位线通道区中的第二部分和通过隔离区的第三连接部。 导电控制栅极通过栅极绝缘体层与浮置栅极分离，并且具有完全设置在第一浮置栅极部分上的第一部分，其中第一浮动栅极部分完全覆盖源极区域和漏极区域之间的空间，第二 设置在第二浮动栅极部分上的部分，其中第二浮动栅极部分不从源极区域延伸到漏极区域，第二控制栅极部分完成源极区域和漏极区域之间的空间的覆盖， 设置在所述第三浮动栅极部分上方的第三连接部分。 编程位线通道接触线和读取位线通道接触线设置在覆盖绝缘体层上并通过覆盖绝缘体层连接到漏极区。

公开(公告)号：US07462906B2

公开(公告)日：2008-12-09

申请号：US11848066

申请日：2007-08-30

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US07348832B2

公开(公告)日：2008-03-25

申请号：US11384846

申请日：2006-03-20

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

摘要翻译： 一种用于从单个外部高压源产生用于存储器件，尤其是非易失性存储器的工作电压的电压产生系统。 在一个实施例中，系统包括用于接收外部电压的输入端子，用于基于外部电压产生高于外部电压的第一高电压的电荷泵，用于将第一高电压调节到第一高电压的第一调节电路 降低预定电压，第二调节电路，用于基于外部电压产生低于外部电压的第二高电压。

公开(公告)号：US20070216471A1

公开(公告)日：2007-09-20

申请号：US11384846

申请日：2006-03-20

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A voltage generation system for generating operating voltages for memory devices, especially non-volatile memories, from a single external high voltage source. In one embodiment, the system comprises an input terminal for receiving an external voltage, a charge pump for producing a first high voltage based on the external voltage to be higher than the external voltage, a first regulating circuit for regulating the first high voltage to a lower predetermined voltage, a second regulating circuit for generating a second high voltage based on the external voltage to be lower than the external voltage.

摘要翻译： 一种用于从单个外部高压源产生用于存储器件，尤其是非易失性存储器的工作电压的电压产生系统。 在一个实施例中，系统包括用于接收外部电压的输入端子，用于基于外部电压产生高于外部电压的第一高电压的电荷泵，用于将第一高电压调节到第一高电压的第一调节电路 降低预定电压，第二调节电路，用于基于外部电压产生低于外部电压的第二高电压。

公开(公告)号：US07102190B2

公开(公告)日：2006-09-05

申请号：US10762166

申请日：2004-01-21

申请人： Hsiang-Tai Lu ,  Chia-Ta Hsieh

发明人： Hsiang-Tai Lu ,  Chia-Ta Hsieh

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A structure for flash memory cells is disclosed, Isolation regions are formed in a semiconductor region separating cells and also separating programming bit line channel regions of a cell from reading bit line charmel regions of a cell. A conductive floating gates has a first portion in the programming bit line channel region of a cell and a second portion in the reading bit line channel region of the cell and a third connecting portion passing over an isolation region. A conductive control gate is separated from the floating gate by an intergate insulator layer and has a first portion entirely disposed over the first floating gate portion, where the first floating gate portion completely covers the space between a source region and a drain region, a second portion disposed over the second floating gate portion, where the second floating gate portion does not extend all the way from a source region to a drain region, the second control gate portion completing the covering of the space between a source region and a drain region and a third connecting portion disposed over the third floating gate portion. A programming bit line channel contact line and a reading bit line channel contact line are disposed over a covering insulator layer and connect to drain regions through the covering insulator layer.

摘要翻译： 公开了一种用于闪速存储器单元的结构，隔离区形成在分离单元的半导体区域中，并且还将单元的编程位线通道区域与单元读取位线charmel区域分离。 导电浮栅具有单元的编程位线沟道区中的第一部分和单元的读取位线通道区中的第二部分和通过隔离区的第三连接部。 导电控制栅极通过栅极绝缘体层与浮置栅极分离，并且具有完全设置在第一浮动栅极部分上的第一部分，其中第一浮动栅极部分完全覆盖源极区域和漏极区域之间的空间，第二部分 设置在第二浮动栅极部分上的部分，其中第二浮动栅极部分不从源极区域延伸到漏极区域，第二控制栅极部分完成源极区域和漏极区域之间的空间的覆盖， 设置在所述第三浮动栅极部分上方的第三连接部分。 编程位线通道接触线和读取位线通道接触线设置在覆盖绝缘体层上并通过覆盖绝缘体层连接到漏极区。