公开(公告)号：US20230056018A1

公开(公告)日：2023-02-23

申请号：US17408942

申请日：2021-08-23

Applicant: Infineon Technologies AG

Inventor： Lin Li ,  Varun Kumar ,  Harald Zweck

IPC: H04L29/06 ,  G06F13/42

Abstract: A traffic anomaly detector of a Peripheral Component Interconnect express (PCIe) system, including filters configured to filter headers of PCIe transaction layer packets (TLPs) based on respective filter criterion; a classifier configured to trigger an event based on one of the filter criterion or a logical combination of a plurality of the filter criteria; an event counter configured to count a number of the events; and a processor configured to detect, based on a value of the event counter, an anomaly in the PCIe TLP traffic.

公开(公告)号：US11321442B2

公开(公告)日：2022-05-03

申请号：US16825896

申请日：2020-03-20

Applicant: Infineon Technologies AG

Inventor： Alexander Zeh ,  Harald Zweck

IPC: G06F21/44 ,  G06F21/60 ,  H04L9/14

Abstract: The present disclosure relates to authenticity and data security for bus-based communication networks in a vehicle. The present disclosure teaches a protocol frame, a sender on data link layer, and a receiver on data link layer providing such authenticity and data security as well as a communication network in a vehicle employing the protocol frame, the sender and the receiver according to the present disclosure.

公开(公告)号：US20210376954A1

公开(公告)日：2021-12-02

申请号：US17333365

申请日：2021-05-28

Applicant: Infineon Technologies AG

Inventor： Wai Keung Frankie Chan ,  Klaus Scheibert ,  Harald Zweck

IPC: H04L1/00 ,  H04L1/20

Abstract: An apparatus for handling an incoming communication data frame containing a plurality of bits is provided. The apparatus may include a plurality of data matchers, each data matcher configured to compare a subset of the plurality of bits of the communication data frame with a predetermined data pattern of a plurality of data patterns and to provide a data matcher output to indicate the result of the data matcher comparison, a plurality of selectors, each selector configured to compare a subset of the data matcher outputs of the plurality of data matchers with a predetermined selection pattern of a plurality of selection patterns and to provide a selector output to indicate the result of the selector comparison, and a frame filter configured to transfer the incoming frame to application logic only if the selector outputs of the plurality of selectors match a predetermined filter pattern, and to also transfer the selector outputs of the plurality of selectors to the application logic.

公开(公告)号：US10191795B2

公开(公告)日：2019-01-29

申请号：US15631544

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Karl Herz ,  Ljudmil Anastasov ,  Harald Zweck

IPC: G06F11/07 ,  G06F5/06 ,  G06F5/12 ,  G06F11/30 ,  G06F13/42 ,  G06F11/34

Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

公开(公告)号：US20140281098A1

公开(公告)日：2014-09-18

申请号：US13803811

申请日：2013-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Frank Hellwig ,  Simon Cottam ,  Harald Zweck

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.

Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括具有系统总线接口并被配置为经由系统总线接口从存储器位置读取模式的总线控制器。 图案比较逻辑将读取图案与至少一个预定图案进行比较。 如果读取模式与预定模式不同，则控制逻辑引起总线控制器处理系统总线接口上的第一条件链接，并且如果读取模式与系统总线接口不同，则总线控制器通过系统总线接口处理第二条件链接 预定模式。