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公开(公告)号：US11544103B2
公开(公告)日：2023-01-03
申请号：US17038183
申请日：2020-09-30
Applicant: Infineon Technologies AG
Inventor： Gerhard Wirrer , Frank Hellwig , Varun Kumar
Abstract: A data processing device is described including one or more processors implementing a plurality of data processing entities, one or more software interrupt nodes and an access register for each software interrupt node. The access register specifies which one or more data processing entities of the plurality of data processing entities is/are each allowed to, as interrupt source data processing entity, trigger an interrupt service request on the software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity. Each software interrupt node is configured to forward an interrupt service request triggered by an interrupt source data processing entity which is allowed to trigger an interrupt service request on the software interrupt node to an interrupt target processing entity.
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Patent Agency Ranking
公开(公告)号：US20210103464A1
公开(公告)日：2021-04-08
申请号：US17038183
申请日：2020-09-30
Applicant: Infineon Technologies AG
Inventor： Gerhard Wirrer , Frank Hellwig , Varun Kumar
Abstract: A data processing device is described including one or more processors implementing a plurality of data processing entities, one or more software interrupt nodes and an access register for each software interrupt node. The access register specifies which one or more data processing entities of the plurality of data processing entities is/are each allowed to, as interrupt source data processing entity, trigger an interrupt service request on the software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity. Each software interrupt node is configured to forward an interrupt service request triggered by an interrupt source data processing entity which is allowed to trigger an interrupt service request on the software interrupt node to an interrupt target processing entity.
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公开(公告)号：US20180101458A1
公开(公告)日：2018-04-12
申请号：US15288434
申请日：2016-10-07
Applicant: Infineon Technologies AG
Inventor： Varun Kumar , Sandeep Naduvalamane , Sumit Khandelwal , Puneetha Mukherjee , Juergen Schaefer
CPC classification number: G06F11/2289 , G06F9/4411 , G06F9/44505 , G06F11/2236 , G06F11/2284 , G06F11/27 , G06F15/781
Abstract: Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.
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公开(公告)号：US12034749B2
公开(公告)日：2024-07-09
申请号：US17408942
申请日：2021-08-23
Applicant: Infineon Technologies AG
Inventor： Lin Li , Varun Kumar , Harald Zweck
CPC classification number: H04L63/1425 , G06F13/4221 , H04L63/1416 , H04L63/1466 , H04L63/166 , G06F2213/0026
Abstract: A traffic anomaly detector of a Peripheral Component Interconnect express (PCIe) system, including filters configured to filter headers of PCIe transaction layer packets (TLPs) based on respective filter criterion; a classifier configured to trigger an event based on one of the filter criterion or a logical combination of a plurality of the filter criteria; an event counter configured to count a number of the events; and a processor configured to detect, based on a value of the event counter, an anomaly in the PCIe TLP traffic.
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公开(公告)号：US20230056018A1
公开(公告)日：2023-02-23
申请号：US17408942
申请日：2021-08-23
Applicant: Infineon Technologies AG
Inventor： Lin Li , Varun Kumar , Harald Zweck
Abstract: A traffic anomaly detector of a Peripheral Component Interconnect express (PCIe) system, including filters configured to filter headers of PCIe transaction layer packets (TLPs) based on respective filter criterion; a classifier configured to trigger an event based on one of the filter criterion or a logical combination of a plurality of the filter criteria; an event counter configured to count a number of the events; and a processor configured to detect, based on a value of the event counter, an anomaly in the PCIe TLP traffic.
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公开(公告)号：US10198332B2
公开(公告)日：2019-02-05
申请号：US15288434
申请日：2016-10-07
Applicant: Infineon Technologies AG
Inventor： Varun Kumar , Sandeep Naduvalamane , Sumit Khandelwal , Puneetha Mukherjee , Juergen Schaefer
Abstract: Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.
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