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公开(公告)号：US12287862B2
公开(公告)日：2025-04-29
申请号：US17981583
申请日：2022-11-07
Applicant: Infineon Technologies AG
Inventor： Sandeep Vangipuram , Glenn Farrall , Albrecht Mayer , Frank Hellwig
Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.
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公开(公告)号：US11888618B2
公开(公告)日：2024-01-30
申请号：US17694768
申请日：2022-03-15
Applicant: Infineon Technologies AG
Inventor： Frank Hellwig
CPC classification number: H04L1/0072 , H04L1/0041 , H04L1/0045 , H04L12/40019
Abstract: A master is provided which is connected to at least one slave via an interface, wherein the at least one master is designed, in a transmission mode to transfer a valid combination of output data and associated error detection data via the interface, and wherein the at least one master is furthermore designed, in a non-transmission mode, to output an invalid combination of output data and associated error detection data in case of an erroneous output request.
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公开(公告)号：US20220303053A1
公开(公告)日：2022-09-22
申请号：US17694768
申请日：2022-03-15
Applicant: Infineon Technologies AG
Inventor： Frank Hellwig
Abstract: A master is provided which is connected to at least one slave via an interface, wherein the at least one master is designed, in a transmission mode to transfer a valid combination of output data and associated error detection data via the interface, and wherein the at least one master is furthermore designed, in a non-transmission mode, to output an invalid combination of output data and associated error detection data in case of an erroneous output request.
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公开(公告)号：US20210279192A1
公开(公告)日：2021-09-09
申请号：US16811081
申请日：2020-03-06
Applicant: Infineon Technologies AG
Inventor： Frank Hellwig
Abstract: A method and apparatus for distributing interconnect bandwidth among master agents. The method includes allocating to each of the master agents a respective portion of the interconnect bandwidth within a time interval; monitoring the master agents to determine if any of the master agents has consumed its allocated portion of interconnect bandwidth within a current time interval; and if a master agent has consumed its allocated portion of interconnect bandwidth within the current time interval, delaying any new access requests from this master agent for a predetermined request delay time within the current time interval.
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公开(公告)号：US20180113816A1
公开(公告)日：2018-04-26
申请号：US15784403
申请日：2017-10-16
Applicant: Infineon Technologies AG
Inventor： Frank Hellwig , Glenn Ashley Farrall , Gerhard Wirrer
CPC classification number: G06F12/145 , G06F12/063 , G06F12/1441 , G06F12/1491 , G06F21/53 , G06F21/6272 , G06F2212/1052 , G06F2212/151
Abstract: A memory protector is configured to evaluate access requests referring to a memory address space. The access requests comprise address parameters referring to addresses of the memory address space. The memory protector comprises an address evaluator, an address results combiner, and a data register. The address evaluator is configured to evaluate whether the address parameters refer to address ranges of a set of address ranges and is configured to provide results regarding the address ranges. The address results combiner is configured to combine results provided by the address evaluator depending on access protection groups to which the address ranges are mapped to. The memory protector is configured to provide access grant results based on combinations provided by the address results combiner. The data register is configured to store data concerning the set of address ranges and concerning a mapping of the address ranges to the access protection groups.
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Patent Agency Ranking
公开(公告)号：US20150242233A1
公开(公告)日：2015-08-27
申请号：US14206033
申请日：2014-03-12
Applicant: Infineon Technologies AG
Inventor： Simon Brewerton , Glenn Farrall , Neil Hastie , Frank Hellwig , Richard Knight , Antonio Vilela
CPC classification number: G06F9/45558 , G06F9/30043 , G06F13/28 , G06F21/71 , G06F21/85 , G06F2009/45583 , G06F2009/45587
Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.
Abstract translation: 本公开涉及用于定义用于控制分布式存储器访问保护系统的处理器安全特权级别的系统和方法。 更具体地，用于在计算机处理系统中访问总线的安全管理程序功能包括用于访问系统存储器的诸如计算机处理单元（CPU）或直接存储器访问（DMY）的模块以及用于存储安全性的存储单元 代码，如处理器状态字（PSW）或配置寄存器（DMA（REG））。 该模块将安全代码分配给处理事务，并且安全代码在模块访问总线时可见。
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公开(公告)号：US20140281098A1
公开(公告)日：2014-09-18
申请号：US13803811
申请日：2013-03-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Frank Hellwig , Simon Cottam , Harald Zweck
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern.
Abstract translation: 一些实施例涉及直接存储器访问（DMA）控制器。 DMA控制器包括具有系统总线接口并被配置为经由系统总线接口从存储器位置读取模式的总线控制器。 图案比较逻辑将读取图案与至少一个预定图案进行比较。 如果读取模式与预定模式不同，则控制逻辑引起总线控制器处理系统总线接口上的第一条件链接，并且如果读取模式与系统总线接口不同，则总线控制器通过系统总线接口处理第二条件链接 预定模式。
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公开(公告)号：US12056253B2
公开(公告)日：2024-08-06
申请号：US17340761
申请日：2021-06-07
Applicant: Infineon Technologies AG
Inventor： Ketan Dewan , Trevor Bird , Simon Cottam , Glenn Ashley Farrall , Darren Galpin , Frank Hellwig , Paul Hubbert , Dietmar Koenig , Shubhendu Mahajan , Sandeep Vangipuram
CPC classification number: G06F21/6218 , G06F21/85 , H03M13/09
Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.
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公开(公告)号：US11544103B2
公开(公告)日：2023-01-03
申请号：US17038183
申请日：2020-09-30
Applicant: Infineon Technologies AG
Inventor： Gerhard Wirrer , Frank Hellwig , Varun Kumar
Abstract: A data processing device is described including one or more processors implementing a plurality of data processing entities, one or more software interrupt nodes and an access register for each software interrupt node. The access register specifies which one or more data processing entities of the plurality of data processing entities is/are each allowed to, as interrupt source data processing entity, trigger an interrupt service request on the software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity. Each software interrupt node is configured to forward an interrupt service request triggered by an interrupt source data processing entity which is allowed to trigger an interrupt service request on the software interrupt node to an interrupt target processing entity.
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公开(公告)号：US20210103464A1
公开(公告)日：2021-04-08
申请号：US17038183
申请日：2020-09-30
Applicant: Infineon Technologies AG
Inventor： Gerhard Wirrer , Frank Hellwig , Varun Kumar
Abstract: A data processing device is described including one or more processors implementing a plurality of data processing entities, one or more software interrupt nodes and an access register for each software interrupt node. The access register specifies which one or more data processing entities of the plurality of data processing entities is/are each allowed to, as interrupt source data processing entity, trigger an interrupt service request on the software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity. Each software interrupt node is configured to forward an interrupt service request triggered by an interrupt source data processing entity which is allowed to trigger an interrupt service request on the software interrupt node to an interrupt target processing entity.
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