公开(公告)号：US20210303482A1

公开(公告)日：2021-09-30

申请号：US17170619

申请日：2021-02-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US10915468B2

公开(公告)日：2021-02-09

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US10359940B2

公开(公告)日：2019-07-23

申请号：US15806240

申请日：2017-11-07

Applicant: INTEL CORPORATION

Inventor： Mark A. Schmisseur ,  Mohan J. Kumar ,  Balint Fleischer ,  Debendra Das Sharma ,  Raj Ramanujan

IPC: G06F3/12 ,  H04L12/24 ,  H04L29/08 ,  G06F3/06

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

公开(公告)号：US09977618B2

公开(公告)日：2018-05-22

申请号：US14142697

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0679 ,  G06F9/5016 ,  G06F2209/5011

Abstract: An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.