公开(公告)号：US20220012189A1

公开(公告)日：2022-01-13

申请号：US17485360

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US20240160585A1

公开(公告)日：2024-05-16

申请号：US18419159

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F12/14 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/00

Abstract: A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

公开(公告)号：US20170004098A1

公开(公告)日：2017-01-05

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Abstract translation: 共享存储器控制器用于通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。 要允许多个独立节点中的每一个访问共享存储器资源的相应部分。 在数据链路上发送互连协议数据和存储器访问协议数据，可以定义和识别互连协议数据和存储器访问协议数据之间的转换。

公开(公告)号：US20210303482A1

公开(公告)日：2021-09-30

申请号：US17170619

申请日：2021-02-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US10915468B2

公开(公告)日：2021-02-09

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US09575895B2

公开(公告)日：2017-02-21

申请号：US14609620

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。

公开(公告)号：US20150143051A1

公开(公告)日：2015-05-21

申请号：US14609620

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。