公开(公告)号：US09778909B2

公开(公告)日：2017-10-03

申请号：US15332721

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

IPC: G06F7/38 ,  G06F7/487 ,  G06F7/483 ,  G06F7/544 ,  G06F7/485 ,  G06F7/499

CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

公开(公告)号：US09374542B2

公开(公告)日：2016-06-21

申请号：US14228684

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Kyriakos Stavrou ,  Pedro Marcuello ,  Grigorios Magklis ,  Javier Carretero Casado ,  Juan Fernandez ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/232

CPC classification number: H04N5/357 ,  H04N5/23229 ,  H04N5/378

Abstract: An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.

Abstract translation: 描述图像信号处理器。 图像信号处理器包括块检查电路。 块检查电路包括比较电路，用于将发光像素值的块与在发光像素值的块之后由图像信号处理器处理的各个发光像素值进行比较。 块检查电路还包括用于在各个发光像素值的块之一与发光像素值的块匹配的情况下将条目记录在表中的电路。 图像信号处理器用于存储发光像素值块的图像信号处理结果，并且将存储的结果作为各个发光像素值的块中的一个的相应结果存在，如果各个发光像素值的块之一 匹配像素值块。

公开(公告)号：US09047014B2

公开(公告)日：2015-06-02

申请号：US14181999

申请日：2014-02-17

Applicant: Intel Corporation

Inventor： Grigorios Magklis ,  Jose Gonzalez ,  Antonio Gonzalez

IPC: G06F1/32 ,  G06F1/06 ,  G06F9/38

CPC classification number: G06F1/06 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract translation: 一种用于缩放微处理器的至少一个时钟域的频率和工作电压的方法和装置。 更具体地，本发明的实施例涉及将微处理器划分为时钟域并且独立于其他时钟域来控制每个时钟域的频率和工作电压的技术。