公开(公告)号：US20190004916A1

公开(公告)日：2019-01-03

申请号：US16026870

申请日：2018-07-03

申请人： Intel Corporation

发明人： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC分类号： G06F11/30 ,  G06F12/0862 ,  G06F11/34

摘要： A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

公开(公告)号：US09374542B2

公开(公告)日：2016-06-21

申请号：US14228684

申请日：2014-03-28

申请人： Intel Corporation

发明人： Kyriakos Stavrou ,  Pedro Marcuello ,  Grigorios Magklis ,  Javier Carretero Casado ,  Juan Fernandez ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou

IPC分类号： H04N5/357 ,  H04N5/378 ,  H04N5/232

CPC分类号： H04N5/357 ,  H04N5/23229 ,  H04N5/378

摘要： An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.

摘要翻译： 描述图像信号处理器。 图像信号处理器包括块检查电路。 块检查电路包括比较电路，用于将发光像素值的块与在发光像素值的块之后由图像信号处理器处理的各个发光像素值进行比较。 块检查电路还包括用于在各个发光像素值的块之一与发光像素值的块匹配的情况下将条目记录在表中的电路。 图像信号处理器用于存储发光像素值块的图像信号处理结果，并且将存储的结果作为各个发光像素值的块中的一个的相应结果存在，如果各个发光像素值的块之一 匹配像素值块。

公开(公告)号：US10157063B2

公开(公告)日：2018-12-18

申请号：US13631402

申请日：2012-09-28

申请人： INTEL CORPORATION

发明人： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzelez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

IPC分类号： G06F9/38 ,  G06F9/30

摘要： A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.