公开(公告)号：US20190035897A1

公开(公告)日：2019-01-31

申请号：US16072313

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Will RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Matthew V. METZ ,  Sean T. MA

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.