公开(公告)号：US10783966B2

公开(公告)日：2020-09-22

申请号：US16593530

申请日：2019-10-04

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

IPC: G11C11/16 ,  G11C13/00 ,  G11C7/04 ,  H01L45/00

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

公开(公告)号：US20190324671A1

公开(公告)日：2019-10-24

申请号：US16373282

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

IPC: G06F3/06 ,  G11C13/00 ,  G06F12/02

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

公开(公告)号：US10360977B2

公开(公告)日：2019-07-23

申请号：US15942329

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan

IPC: G11C16/04 ,  G11C13/00

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.