公开(公告)号：US20190324671A1

公开(公告)日：2019-10-24

申请号：US16373282

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

IPC: G06F3/06 ,  G11C13/00 ,  G06F12/02

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

公开(公告)号：US10185818B2

公开(公告)日：2019-01-22

申请号：US15438346

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

IPC: G06F7/58 ,  G06F21/44 ,  G09C1/00 ,  G11C13/00 ,  H04L9/08 ,  H04L9/32

Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.

公开(公告)号：US20170161488A1

公开(公告)日：2017-06-08

申请号：US15438346

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

IPC: G06F21/44 ,  G11C13/00 ,  G06F7/58

CPC classification number: G06F21/44 ,  G06F7/58 ,  G06F7/588 ,  G09C1/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.

公开(公告)号：US10248351B1

公开(公告)日：2019-04-02

申请号：US15721388

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

公开(公告)号：US10884640B2

公开(公告)日：2021-01-05

申请号：US16373282

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

公开(公告)号：US20190102099A1

公开(公告)日：2019-04-04

申请号：US15721388

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

IPC: G06F3/06 ,  G11C13/00

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.