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    Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources
    11.
    发明授权
    Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources 有权

    公开(公告)号：US10296347B2

    公开(公告)日：2019-05-21

    申请号：US15340916

    申请日：2016-11-01

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Robert Valentine ,  Julian C. Horn ,  Mark J. Charney

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.

    System-on-chip (SoC) to perform a bit range isolation instruction
    15.
    发明授权
    System-on-chip (SoC) to perform a bit range isolation instruction 有权

    公开(公告)号：US10579380B2

    公开(公告)日：2020-03-03

    申请号：US14568754

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  Elmoustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    PROCESSOR TO PERFORM A BIT RANGE ISOLATION INSTRUCTION
    16.
    发明申请
    PROCESSOR TO PERFORM A BIT RANGE ISOLATION INSTRUCTION 审中-公开
    处理器执行一个位格式隔离指令

    公开(公告)号：US20150100760A1

    公开(公告)日：2015-04-09

    申请号：US14568725

    申请日：2014-12-12

    Applicant: Intel Corporation

    Inventor： Maxim Loktyukhin ,  Eric W Mahurin ,  Bret L Toll ,  Martin G Dixon ,  Sean P Mirkes ,  David L Kreitzer ,  ELMOUSTAPHA OULD-AHMED-VALL ,  Vinodh Gopal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    Abstract translation: 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

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