公开(公告)号：US11741227B2

公开(公告)日：2023-08-29

申请号：US17354125

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Michael Berger ,  Xiaoyu Ruan ,  Purushottam Goel ,  Mahesh Natu ,  Bharat Pillilli

IPC: G06F21/55 ,  G06F21/57

CPC classification number: G06F21/556 ,  G06F21/554 ,  G06F21/572

Abstract: An apparatus comprising a computer platform, including a central processing unit (CPU) comprising a first security engine to perform security operations at the CPU and a chipset comprising a second security engine to perform security operations at the chipset, wherein the first security engine and the second security engine establish a secure channel session between the CPU and the chipset to secure data transmitted between the CPU and the chipset.

公开(公告)号：US11568048B2

公开(公告)日：2023-01-31

申请号：US17131985

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Nivedita Aggarwal ,  Zhenyu Zhu ,  Michael Berger

IPC: G06F21/55 ,  G06F11/14 ,  G06F13/42 ,  G06F21/57 ,  H04L9/32 ,  G06F11/07 ,  G06F11/20 ,  H04L9/08

Abstract: An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

公开(公告)号：US20210117539A1

公开(公告)日：2021-04-22

申请号：US17131985

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Nivedita Aggarwal ,  Zhenyu Zhu ,  Michael Berger

IPC: G06F21/55 ,  G06F21/57 ,  H04L9/32 ,  G06F11/14 ,  G06F13/42

Abstract: An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

公开(公告)号：US20160179585A1

公开(公告)日：2016-06-23

申请号：US14576019

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Michael Berger ,  Khee Wooi Lee ,  Mukesh Kataria

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F9/4403 ,  G06F11/00 ,  G06F15/17 ,  G06F15/17325 ,  G06F15/17337

Abstract: A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.

Abstract translation: 本文公开了一种用于执行只写入处理器复位同步的方法和装置。 在一个实施例中，处理单元包括：通信单元，用于向第二处理单元发送信息; 存储器，用于存储复位同步信息和消息信息; 以及处理逻辑，用于基于在存储器中设置的位指示，在其自身和第二处理单元之间执行只写复位同步。