公开(公告)号：US11568048B2

公开(公告)日：2023-01-31

申请号：US17131985

申请日：2020-12-23

申请人： Intel Corporation

发明人： Nivedita Aggarwal ,  Zhenyu Zhu ,  Michael Berger

IPC分类号： G06F21/55 ,  G06F11/14 ,  G06F13/42 ,  G06F21/57 ,  H04L9/32 ,  G06F11/07 ,  G06F11/20 ,  H04L9/08

摘要： An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

公开(公告)号：US11119704B2

公开(公告)日：2021-09-14

申请号：US16367608

申请日：2019-03-28

申请人： Intel Corporation

发明人： Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

IPC分类号： G06F3/06 ,  G06F13/38 ,  G06F9/54

摘要： In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

公开(公告)号：US20210117539A1

公开(公告)日：2021-04-22

申请号：US17131985

申请日：2020-12-23

申请人： Intel Corporation

发明人： Nivedita Aggarwal ,  Zhenyu Zhu ,  Michael Berger

IPC分类号： G06F21/55 ,  G06F21/57 ,  H04L9/32 ,  G06F11/14 ,  G06F13/42

摘要： An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

公开(公告)号：US20210117365A1

公开(公告)日：2021-04-22

申请号：US17134293

申请日：2020-12-26

申请人： Intel Corporation

发明人： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC分类号： G06F13/42 ,  G06F1/08 ,  G06F1/24 ,  G06F1/3287 ,  G06F9/4401

摘要： An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

公开(公告)号：US10324867B2

公开(公告)日：2019-06-18

申请号：US15482646

申请日：2017-04-07

申请人： Intel Corporation

发明人： Sivakumar Radhakrishnan ,  Mahesh S. Natu ,  Zhenyu Zhu ,  Malay Trivedi ,  Randall L. Albion ,  Chris Ruffin

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/24 ,  G06F3/06

摘要： Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.

公开(公告)号：US20180095740A1

公开(公告)日：2018-04-05

申请号：US15282863

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Karunakara Kotary ,  Basavaraj B. Astekar ,  Zhenyu Zhu

IPC分类号： G06F9/445

CPC分类号： G06F8/61 ,  G06F8/60 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/445

摘要： In one example, a system on a chip can include an embedded controller and a security controller that can detect, during an initialization process, a request for embedded controller firmware stored in block storage from the embedded controller via a transmission link. The security controller can also retrieve the embedded controller firmware stored in the block storage and transmit the embedded controller firmware to the embedded controller via the transmission link.

公开(公告)号：US20170153687A1

公开(公告)日：2017-06-01

申请号：US15074774

申请日：2016-03-18

申请人： Intel Corporation

发明人： Zhenyu Zhu ,  Anoop Mukker ,  Daniel Nemiroff ,  Nobuyuki Suzuki ,  David W. Vogel

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3234 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/325 ,  Y02D50/20

摘要： An example method for power management of a user interface includes initiating a low power entry at a data lane of the user interface. The method further includes coordinating with a peripheral device to enter into an ultra-low power state. The peripheral device is to initiate a low power entry at the clock lane to enter the user interface into an ultra-low power state in response to detecting the low power entry at the data lane.

公开(公告)号：US20220317855A1

公开(公告)日：2022-10-06

申请号：US17849282

申请日：2022-06-24

申请人： Intel Corporation

发明人： Zhenyu Zhu ,  Satheesh Chellappan ,  Antonio Cheng ,  Kar Leong Wong

IPC分类号： G06F3/041 ,  G06N3/02

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed to process touch data. An example apparatus includes machine learning accelerator circuitry to execute a machine learning algorithm on touch data from touch sensor circuitry; and determine, based on an output of the machine learning algorithm, whether a touch input corresponding to the touch data was intentional; transceiver circuitry to, after a determination that the touch input was intentional, provide touch coordinates to memory; and processor circuitry to, after the determination that the touch input was intentional: access the touch coordinates in the memory; and perform an action based on the touch coordinates.

公开(公告)号：US11163659B2

公开(公告)日：2021-11-02

申请号：US16394929

申请日：2019-04-25

申请人： Intel Corporation

发明人： Aditya Bhutada ,  Zhenyu Zhu ,  Mazen Gedeon

IPC分类号： G06F11/22 ,  G06F11/07

摘要： Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI primary device to an eSPI secondary device. In embodiments, the eSPI primary device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI primary device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI primary device and the eSPI secondary device. Other embodiments may be described and/or claimed.

公开(公告)号：US11086812B2

公开(公告)日：2021-08-10

申请号：US14998222

申请日：2015-12-26

申请人： Intel Corporation

发明人： Mikal C. Hunsaker ,  Shaun M. Conrad ,  Zhenyu Zhu ,  Navtej Singh

IPC分类号： G06F13/42 ,  G06F13/362 ,  G06F13/40

摘要： An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.