公开(公告)号：US20180262479A1

公开(公告)日：2018-09-13

申请号：US15976207

申请日：2018-05-10

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent J. Zimmer ,  Shahrok Shahidzadeh ,  Mohan J. Kumar ,  Sergiu D. Ghetie

IPC: H04L29/06 ,  G06F21/57 ,  G06F21/34

CPC classification number: H04L63/107 ,  G06F21/34 ,  G06F21/575 ,  G06F2221/2111

Abstract: Technologies for verifying authorized operation includes an administration server to query a dual-headed identification device of a server for identification data indicative of an identity of the server. The dual-headed identification device includes a wired communication circuit, a wireless communication circuit, and a memory having the identification data stored therein. The administration server further obtains the identification data from the dual-headed identification device of the server, determines a context of the server, and determines whether boot of the server is authorized based on the context of the server, the identification data of the server, and a security policy of the server.

公开(公告)号：US11526352B2

公开(公告)日：2022-12-13

申请号：US16932682

申请日：2020-07-17

Applicant: Intel Corporation

Inventor： Sergiu D. Ghetie

IPC: G06F9/24 ,  G06F12/0875 ,  G06F1/3203

Abstract: Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

公开(公告)号：US11429385B2

公开(公告)日：2022-08-30

申请号：US16236434

申请日：2018-12-29

Applicant: Intel Corporation

Inventor： Sergiu D. Ghetie

IPC: G06F9/24 ,  G06F12/0875 ,  G06F1/3203 ,  G06F9/26

Abstract: Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for: storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

公开(公告)号：US11218322B2

公开(公告)日：2022-01-04

申请号：US15719375

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Sergiu D. Ghetie ,  Neeraj S. Upasani ,  Chukwunenye S. Nnebe ,  Won Lee ,  Shaila R. Murty ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  David T. Mayo ,  Scott P. Bobholz ,  Vinila Rose ,  Wojciech S. Powiertowski

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/14 ,  G06Q10/08 ,  H04L9/30

Abstract: Techniques and apparatuses for issuance of license upgrades for hardware components in the field, as well as the hardware components, are described. In one embodiment, for example an apparatus may include processor circuitry and memory in communication with the processor circuitry, wherein the memory contains a configuration data block and license data block, the configuration data block being read from the memory via a licensing apparatus and the licensing data block being written to the memory by the licensing apparatus. The processor may include executable code to process the licensing data block to facilitate an upgrade of the capabilities of the processor circuitry.

公开(公告)号：US20200348939A1

公开(公告)日：2020-11-05

申请号：US16932682

申请日：2020-07-17

Applicant: Intel Corporation

Inventor： Sergiu D. Ghetie

IPC: G06F9/38 ,  G06F12/0875

Abstract: Hardware processors and methods for extended microcode patching through on-die and off-die secure storage are described. In one embodiment, the additional storage resources used for storing micro-operations are section(s) of a cache that are unused at runtime and/or unused by a configuration of a processor. For example, the additional storage resources may be a section of a cache that is used to store context information from a core when the core is transitioned to a power state that shuts off voltage to the core. Non-limiting examples of such sections are one or more sections for storage of context information for a transition of a thread to idle or off, storage of context information for a transition of a core for a multiple core processor to idle or off, or storage of coherency information for a transition of a cache coherency circuit (e.g., cache box (CBo)) to idle or off.

公开(公告)号：US10318748B2

公开(公告)日：2019-06-11

申请号：US15283087

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Neeraj S. Upasani ,  David P. Turley ,  Sergiu D. Ghetie ,  Zhangping Chen ,  Jason G. Sandri

IPC: G06F21/62 ,  G06F21/60 ,  G11C7/24 ,  G11C7/10 ,  G11C17/18 ,  G11C29/00

Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

公开(公告)号：US20190065261A1

公开(公告)日：2019-02-28

申请号：US15859366

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ananth S. Narayan ,  Sagar V. Dalvi ,  Mrittika Ganguli ,  Sergiu D. Ghetie

IPC: G06F9/50 ,  G06F11/34 ,  G06F11/30 ,  G06F17/30

Abstract: Technologies for providing in-processor workload phase detection include a sled having a compute engine, which itself includes a performance monitor unit. The compute engine obtains telemetry data from the performance monitor unit. The performance monitor unit produces telemetry data indicative of performance metrics of the sled during execution of one or more workloads. The telemetry data is indicative of a resource utilization and workload performance by the sled as the workloads are executed. The compute engine determines, from a lookup table indicative of resource utilization phases, a resource utilization phase based on the obtained telemetry data. A workload fingerprint is updated based on the determined resource utilization phase, and the workload fingerprint is output. Other embodiments are also described and claimed.