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公开(公告)号：US12236243B2
公开(公告)日：2025-02-25
申请号：US18138591
申请日：2023-04-24
Applicant: Intel Corporation
Inventor： Jason W. Brandt , Deepak K. Gupta , Rodrigo Branco , Joseph Nuzman , Robert S. Chappell , Sergiu Ghetie , Wojciech Powiertowski , Jared W. Stark, IV , Ariel Sabba , Scott J. Cape , Hisham Shafi , Lihu Rappoport , Yair Berger , Scott P. Bobholz , Gilad Holzstein , Sagar V. Dalvi , Yogesh Bijlani
Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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公开(公告)号：US09760155B2
公开(公告)日：2017-09-12
申请号：US14960693
申请日：2015-12-07
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
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公开(公告)号：US20140229750A1
公开(公告)日：2014-08-14
申请号：US13976682
申请日：2012-03-13
Applicant: INTEL CORPORATION
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Samuel W. Ho , Scott P. Bobholz , Chris Poirier
IPC: G06F1/32
CPC classification number: G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/152 , Y02D10/22 , Y02D10/24
Abstract: A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.
Abstract translation: 一种处理器中每个核心性能状态的方法和装置。 每个核心性能状态（PCPS）是指在不同的电压和/频率点对各个内核的并行运行。 在本发明的一个实施例中，处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。 功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。 通过允许其内核具有每个核心性能状态配置，处理器能够降低其功耗并提高其性能。
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公开(公告)号：US20230342156A1
公开(公告)日：2023-10-26
申请号：US18138591
申请日：2023-04-24
Applicant: Intel Corporation
Inventor： Jason W. Brandt , Deepak K. Gupta , Rodrigo Branco , Joseph Nuzman , Robert S. Chappell , Sergiu Ghetie , Wojciech Powiertowski , Jared W. Stark, IV , Ariel Sabba , Scott J. Cape , Hisham Shafi , Lihu Rappoport , Yair Berger , Scott P. Bobholz , Gilad Holzstein , Sagar V. Dalvi , Yogesh Bijlani
CPC classification number: G06F9/3844 , G06F9/30101
Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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公开(公告)号：US11635965B2
公开(公告)日：2023-04-25
申请号：US16177028
申请日：2018-10-31
Applicant: Intel Corporation
Inventor： Jason W. Brandt , Deepak K. Gupta , Rodrigo Branco , Joseph Nuzman , Robert S. Chappell , Sergiu D. Ghetie , Wojciech Powiertowski , Jared W. Stark, IV , Ariel Sabba , Scott J. Cape , Hisham Shafi , Lihu Rappoport , Yair Berger , Scott P. Bobholz , Gilad Holzstein , Sagar V. Dalvi , Yogesh Bijlani
Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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Patent Agency Ranking
公开(公告)号：US10203741B2
公开(公告)日：2019-02-12
申请号：US15048189
申请日：2016-02-19
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
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7.发明授权公开(公告)号：US09141426B2
公开(公告)日：2015-09-22
申请号：US13631831
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Matthew M. Bace , A Leonard Brown , Ian M. Steiner , Vivek Garg , Eric Dehaemer , Scott P. Bobholz
CPC classification number: G06F9/4881 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F11/3409 , G06F2201/865 , G06F2201/88 , Y02D10/126 , Y02D10/152 , Y02D10/171
Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.
Abstract translation: 描述了一种包括处理核心和用于处理核心的多个计数器的处理器。 多个计数器将对由处理核心支持的多个线程中的每个线程计数第一值和第二值。 第一个值反映已经为第一个值对应的线程请求了非睡眠状态的多个周期，以及反映已经请求非睡眠状态和最高性能状态的周期数的第二个值 第二个值的相应线程。 第一个值的相应线程和第二个值的相应线程是相同的线程。
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公开(公告)号：US11218322B2
公开(公告)日：2022-01-04
申请号：US15719375
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： Sergiu D. Ghetie , Neeraj S. Upasani , Chukwunenye S. Nnebe , Won Lee , Shaila R. Murty , Arkadiusz Berent , Vasuki Chilukuri , David T. Mayo , Scott P. Bobholz , Vinila Rose , Wojciech S. Powiertowski
Abstract: Techniques and apparatuses for issuance of license upgrades for hardware components in the field, as well as the hardware components, are described. In one embodiment, for example an apparatus may include processor circuitry and memory in communication with the processor circuitry, wherein the memory contains a configuration data block and license data block, the configuration data block being read from the memory via a licensing apparatus and the licensing data block being written to the memory by the licensing apparatus. The processor may include executable code to process the licensing data block to facilitate an upgrade of the capabilities of the processor circuitry.
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9.发明申请HARDWARE PROCESSORS AND METHODS TO PERFORM SELF-MONITORING DIAGNOSTICS TO PREDICT AND DETECT FAILURE 审中-公开硬件处理器和执行自我诊断诊断和检测故障的方法公开(公告)号：US20160378628A1
公开(公告)日：2016-12-29
申请号：US14752821
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Hang T. Nguyen , Gordon McFadden , Travis J. White , Scott P. Bobholz , Edwin Verplanke , Steven C. Franks , Vivek Garg , Ashok Raj , Guy G. Sotomayor , Jose A. Vargas , Pradeepsunder Ganesh , Stephen T. Palermo
IPC: G06F11/273 , G06F11/22
CPC classification number: G06F11/2236 , G06F11/008 , G06F11/27
Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.
Abstract translation: 描述了执行自我监视诊断以预测和检测故障的硬件处理器和方法。 在一个实施例中，硬件处理器包括多个核心，以及诊断硬件单元，用于在运行时间隔离所述多个核心的核心，在隔离的核心上执行压力测试，从所述核心的结果中确定压力因素 压力测试，并将应力因子存储在数据存储设备中。
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公开(公告)号：US20160085293A1
公开(公告)日：2016-03-24
申请号：US14960693
申请日：2015-12-07
Applicant: Intel Corporation
Inventor： Malini K. Bhandaru , Eric J. Dehaemer , Scott P. Bobholz , Raghunandan Makaram , Vivek Garg
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3225 , G06F1/3234 , G06F1/3243 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，多核处理器包括可独立执行指令的核心，每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。
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