公开(公告)号：US12229269B2

公开(公告)日：2025-02-18

申请号：US17127122

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Chinmay Ashok ,  Vasudevan Srinivasan ,  Atanas K. Iwanow ,  Martin G. Dixon ,  Scott J. Cape ,  Scott Bobholz ,  David T. Mayo ,  Vinila Rose ,  Lorie Wigle ,  Jason Kennedy

IPC: G06F21/57 ,  G06F21/10 ,  G06F21/44

Abstract: Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

公开(公告)号：US11953962B2

公开(公告)日：2024-04-09

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/52 ,  G06F13/20 ,  G06F1/3287 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US20230131521A1

公开(公告)日：2023-04-27

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F1/3203 ,  G06F9/50 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US11579944B2

公开(公告)日：2023-02-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/50 ,  G06F9/52 ,  G06F13/20 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/3287

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US11218322B2

公开(公告)日：2022-01-04

申请号：US15719375

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Sergiu D. Ghetie ,  Neeraj S. Upasani ,  Chukwunenye S. Nnebe ,  Won Lee ,  Shaila R. Murty ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  David T. Mayo ,  Scott P. Bobholz ,  Vinila Rose ,  Wojciech S. Powiertowski

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/14 ,  G06Q10/08 ,  H04L9/30

Abstract: Techniques and apparatuses for issuance of license upgrades for hardware components in the field, as well as the hardware components, are described. In one embodiment, for example an apparatus may include processor circuitry and memory in communication with the processor circuitry, wherein the memory contains a configuration data block and license data block, the configuration data block being read from the memory via a licensing apparatus and the licensing data block being written to the memory by the licensing apparatus. The processor may include executable code to process the licensing data block to facilitate an upgrade of the capabilities of the processor circuitry.

公开(公告)号：US20190079806A1

公开(公告)日：2019-03-14

申请号：US16190806

申请日：2018-11-14

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F9/52 ,  G06F13/20 ,  G06F9/50 ,  G06F1/28

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.