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公开(公告)号：US12047485B2
公开(公告)日：2024-07-23
申请号：US17132365
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
CPC classification number: H04L9/003 , G06F1/26 , H04L9/0631 , H04L2209/08
Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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公开(公告)号：US11768966B2
公开(公告)日：2023-09-26
申请号：US17930326
申请日：2022-09-07
Applicant: Intel Corporation
Inventor： Vikram Suresh , Raghavan Kumar , Sanu Mathew
CPC classification number: G06F21/75 , G06F21/31 , G06F21/79 , G06F2221/2103
Abstract: A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.
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13.发明授权公开(公告)号：US11456877B2
公开(公告)日：2022-09-27
申请号：US16456187
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Sanu Mathew , Manoj Sastry , Santosh Ghosh , Vikram Suresh , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments. A method includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
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公开(公告)号：US20220200784A1
公开(公告)日：2022-06-23
申请号：US17132365
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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公开(公告)号：US10825511B2
公开(公告)日：2020-11-03
申请号：US16417538
申请日：2019-05-20
Applicant: Intel Corporation
Inventor： Vivek De , Sanu Mathew , Sudhir Satpathy , Vikram Suresh , Raghavan Kumar
IPC: G11C11/419 , H04L9/32 , G09G5/00 , G06F7/58
Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.
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Patent Agency Ranking
16.发明授权公开(公告)号：US10755242B2
公开(公告)日：2020-08-25
申请号：US15274200
申请日：2016-09-23
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sudhir Satpathy , Sanu Mathew
Abstract: A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi−1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.
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17.发明申请公开(公告)号：US20190319799A1
公开(公告)日：2019-10-17
申请号：US16455921
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Manoj Sastry , Santosh Ghosh , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.
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公开(公告)号：US11770262B2
公开(公告)日：2023-09-26
申请号：US17568919
申请日：2022-01-05
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Vikram Suresh , Santosh Ghosh , Manoj Sastry , Sanu Mathew , Raghavan Kumar
CPC classification number: H04L9/3247 , H04L9/085 , H04L9/0852 , H04L9/50
Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
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公开(公告)号：US20220123943A1
公开(公告)日：2022-04-21
申请号：US17562461
申请日：2021-12-27
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Manoj Sastry , Santosh Ghosh , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.
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公开(公告)号：US11205017B2
公开(公告)日：2021-12-21
申请号：US16456339
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Rafael Misoczki , Santosh Ghosh , Raghavan Kumar , Manoj Sastry , Andrew H. Reinders
Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
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