公开(公告)号：US20160285997A1

公开(公告)日：2016-09-29

申请号：US14778026

申请日：2014-06-26

Applicant: Xiangbin Wu ,  Shunyu Zhu ,  Yingzhe Shen ,  Tin-Fook Ngai ,  Intel Corporation

Inventor： Xiangbin Wu ,  Shunyu Zhu ,  Yingzhe Shen ,  Tin-Fook Ngai

IPC: H04L29/08 ,  H04L29/06 ,  G06F17/30

CPC classification number: H04L67/2852 ,  G06F17/30902 ,  H04L67/10 ,  H04L67/42

Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a client device of the memcached system may include memory and one or more processors coupled with the memory. Further, the client device may include memcached logic configured to receive a request to Get or Set a value corresponding to a key in the memcached system, determine, in response to the receive, whether the key results in a hit in a local cache maintained in memory by the memcached logic, and service the Get or Set request based at least in part on whether a result of the determine indicates the key results in a hit in the local cache. In embodiments, a server of the memcached system may include complement memcached logic to server a Get, Set or an Update request. Other embodiments may be described and/or claimed.

Abstract translation: 本文公开了与memcached系统相关联的装置，方法和存储介质。 在实施例中，memcached系统的客户端设备可以包括存储器和与存储器耦合的一个或多个处理器。 此外，客户端设备可以包括被配置为接收获取或设置与memcached系统中的密钥对应的值的请求的memcached逻辑，响应于接收确定密钥是否导致本地高速缓存中的命中被保持在 存储器通过memcached逻辑，并且至少部分地基于确定的结果是否指示在本地高速缓存中的命中的关键结果来服务Get或Set请求。 在实施例中，memcached系统的服务器可以包括用于服务Get，Set或Update请求的补码memcached逻辑。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11798191B2

公开(公告)日：2023-10-24

申请号：US16832094

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Ignacio Alvarez ,  Cornelius Buerkle ,  Maik Sven Fox ,  Florian Geissler ,  Ralf Graefe ,  Yiwen Guo ,  Yuqing Hou ,  Fabian Oboril ,  Daniel Pohl ,  Alexander Carl Unnervik ,  Xiangbin Wu

IPC: G06T7/80 ,  G01S13/931 ,  G01S13/86 ,  G01S7/40 ,  G01S7/497 ,  G01S17/931

CPC classification number: G06T7/80 ,  G01S7/40 ,  G01S7/4972 ,  G01S13/865 ,  G01S13/867 ,  G01S13/931 ,  G01S17/931 ,  G06T2207/30236 ,  G06T2207/30248 ,  G06T2207/30252 ,  G06T2207/30261

Abstract: A sensor calibrator comprising one or more processors configured to receive sensor data representing a calibration pattern detected by a sensor during a period of relative motion between the sensor and the calibration pattern in which the sensor or the calibration pattern move along a linear path of travel; determine a calibration adjustment from the plurality of images; and send a calibration instruction for calibration of the sensor according to the determined calibration adjustment. Alternatively, a sensor calibration detection device, comprising one or more processors, configured to receive first sensor data detected during movement of a first sensor along a route of travel; determine a difference between the first sensor data and stored second sensor data; and if the difference is outside of a predetermined range, switch from a first operational mode to a second operational mode.

公开(公告)号：US11113159B2

公开(公告)日：2021-09-07

申请号：US16616905

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Zhiyuan Zhang ,  Xiangbin Wu ,  Xinxin Zhang ,  Qianying Zhu ,  Haitao Ji ,  Yingzhe Shen

IPC: G06F11/14 ,  G06F12/16 ,  G06F17/40 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

Abstract: An embodiment of a memory apparatus may include a logger to log memory access data in persistent storage media, a log indexer communicatively coupled to the logger to index the memory access log data in an index table in a system memory, and a key compressor communicatively coupled to the log indexer to compress an index key for the index table. Other embodiments are disclosed and claimed.

公开(公告)号：US20200257609A1

公开(公告)日：2020-08-13

申请号：US16787333

申请日：2020-02-11

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Andrew V. Anderson ,  Richard A. Uhlig ,  David M. Durham ,  Ronak Singhal ,  Xiangbin Wu ,  Sailesh Kottapalli

IPC: G06F11/34 ,  G06F9/455 ,  G06F13/24 ,  G06F11/30

Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.

公开(公告)号：US10581997B2

公开(公告)日：2020-03-03

申请号：US15549146

申请日：2015-03-05

Applicant: INTEL CORPORATION

Inventor： Shunyu Zhu ,  Xiangbin Wu ,  Zhiyuan Zhang ,  Xinxin Zhang ,  Qianying Zhu

IPC: G06F13/00 ,  H04L29/08 ,  G06F16/958 ,  G06F16/21 ,  G06F16/22

Abstract: Examples may include techniques for storing or accessing a key-value (KV) item stored in a memory that is part of a memcached system. A KV server coupled with a network input/output device may be capable of allocating one or more item slots from the memory and indicating to logic or features of the network input/output device whether the KV item is stored in a single allocated item slot of the memory, accessible via multiple allocated item slots of the memory or whether the KV item is being updated.

公开(公告)号：US10306673B2

公开(公告)日：2019-05-28

申请号：US15300042

申请日：2014-05-12

Applicant: Intel Corporation

Inventor： Zhiyuan Zhang ,  Qianying Zhu ,  Xinxin Zhang ,  Shunyu Zhu ,  Xiangbin Wu ,  Xuebin Yang ,  Senjie Zhang ,  Guangjie Li ,  Xu Zhang

IPC: H04W74/00 ,  H04L27/26 ,  H04L5/00 ,  H04W56/00 ,  H04W74/08 ,  H03M7/30 ,  H04W88/08

Abstract: A front-end unit that operates within a C-RAN architecture to perform the functions of cellular signal processing and resource selection between an RRU and the BBU pool network is described. The front-end unit supports flexible load migration and CoMP (coordinated multipoint) in the CRAN BBU while also reducing data transmission within the BBU pool network or between the BBU pool network and the RRU.

公开(公告)号：US10146702B2

公开(公告)日：2018-12-04

申请号：US14911353

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Xiangbin Wu ,  Gansha Wu

IPC: H04L9/14 ,  G06F12/14 ,  G06F17/30 ,  G06F12/0813 ,  H04L9/32 ,  H04L29/06 ,  H04L29/08

Abstract: Apparatuses, methods and storage medium associated with a memcached system are disclosed herewith. In embodiments, a server apparatus may include memory; one or more processors; a network interface card to support remote memory direct access of the memory, by a client device, for a value of a key using an address that is a morph address of a physical address of a storage location of the memory having the value; and server side memcached logic operated by the one or more processors. Other embodiments may be described and/or claimed.