公开(公告)号：US10970805B2

公开(公告)日：2021-04-06

申请号：US15779368

申请日：2016-12-06

Applicant: INTEL CORPORATION

Inventor： Yuanyuan Li ,  Hai Bai ,  Guizi Li

IPC: G06F15/16 ,  G06T1/20 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50

Abstract: A system and method for distributed computing including a compute node having a graphics processing unit (GPU) to execute tasks of a distributed computing job. A distributed-computing programming framework executes the tasks on the compute node. A GPU-daemon process shares GPU resources between the tasks executing on the GPU of the compute node.

公开(公告)号：US11698964B2

公开(公告)日：2023-07-11

申请号：US16650643

申请日：2017-12-13

Applicant: INTEL CORPORATION

Inventor： Danyu Bi ,  Salmin Sultana ,  Yuanyuan Li ,  Yong Jiang ,  Pramod Pesara ,  Selvakumar Panneer ,  Ravi Sahita

IPC: G06F21/56 ,  G06F9/448 ,  G06F9/30 ,  G06F11/36 ,  G06F12/1009 ,  H04L9/40

CPC classification number: G06F21/56 ,  G06F9/30061 ,  G06F9/448 ,  G06F11/3636 ,  G06F12/1009 ,  G06F21/566 ,  H04L63/145 ,  H04L63/1441

Abstract: A system for detecting malware includes a processor to collect processor trace information corresponding to an application being executed by the processor (202). The processor can also detect an invalid indirect branch instruction from the processor trace information (204) and detect at least one malware instruction being executed by the application in response to analyzing modified memory values corresponding to the invalid indirect branch (206). Additionally, the processor can block the application from accessing or modifying memory (208).

公开(公告)号：US20180329762A1

公开(公告)日：2018-11-15

申请号：US15778109

申请日：2015-12-25

Applicant: Intel Corporation

Inventor： Yuanyuan Li ,  Yuting Yang ,  Yong Jiang ,  Yao Wang

IPC: G06F9/54

CPC classification number: G06F9/542 ,  G06F9/44 ,  G06F9/4411

Abstract: Methods and apparatus relating to event-driven framework for GPU (Graphics Processing Unit) programming are described. In an embodiment, event-driven logic receives a signal that indicates detection of an event by a device. Memory stores information corresponding to a kernel that is to be associated with the event. The event-driven logic causes a Graphics Processing Unit (GPU) to execute the kernel to process one or more operations in response to the event. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170364440A1

公开(公告)日：2017-12-21

申请号：US15525033

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Jianghong Du ,  Yong Jiang ,  Lei Shen ,  Yuanyuan Li

IPC: G06F12/0804

Abstract: Described is a machine-readable storage medium having instructions stored thereon, that when executed, cause a processor to perform a method which comprises: grouping two or more work groups to form a super-workgroup; and partitioning a portion of a memory space into one or more super-shared local memories (Super-SLMs), wherein the memory space shared within the super-workgroup forms at least one Super-SLM of the one or more Super-SLMs. Described is an apparatus which comprises: a plurality of execution units; a cache memory having a portion characterized as a SLM which is shared with the plurality of execution units at least one of which is to operate on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units is to operate on the different work groups.

公开(公告)号：US11989580B2

公开(公告)日：2024-05-21

申请号：US17197304

申请日：2021-03-10

Applicant: Intel Corporation

Inventor： Yong Jiang ,  Yuanyuan Li ,  Jianghong Du ,  Kuilin Chen ,  Thomas A. Tetzlaff

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/52 ,  G06T1/20 ,  G06F8/41

CPC classification number: G06F9/4843 ,  G06F9/3009 ,  G06F9/522 ,  G06T1/20 ,  G06F8/458 ,  G06F9/30087

Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.

公开(公告)号：US20220359030A1

公开(公告)日：2022-11-10

申请号：US17866715

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Yuanyuan Li ,  Rakan Maddah ,  Prashant S. Damle ,  Dany-Sebastien Ly-Gagnon ,  Lunkai Zhang

IPC: G11C29/10 ,  G11C29/12 ,  G11C29/18

Abstract: Systems, apparatuses, and methods provide for technology performs write current adjustment management in crosspoint persistent memory structures. Such technology determines whether to adjust a base current in response to a sampling of write-and-read operations on a set of addresses in a crosspoint persistent memory; determines whether a test current reduces a number of bit fails in response to a determination of whether to adjust the base current; and adjusts the base current based on the test current in response to a determination that the test current reduces the number of bit fails.