公开(公告)号：US08019979B2

公开(公告)日：2011-09-13

申请号：US11854003

申请日：2007-09-12

申请人： Jeffrey W. Calder ,  Tong Sun

发明人： Jeffrey W. Calder ,  Tong Sun

IPC分类号： G06F9/34 ,  G06F9/40

CPC分类号： G06F9/3885 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/3846

摘要： An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register.

摘要翻译： 公开了一种实现分支密集算法的装置。 该装置包括包含多个ALU和多个结果寄存器的处理器。 每个结果寄存器具有保护输入，允许ALU在接收到保护输入端的选择信号时将结果写入寄存器。 用逻辑动态编程查找表以实现即将到来的程序代码的分支部分。 在对代码的分支部分的分支条件进行评估时，查找表基于分配条件语句和编入查找表中的真值表的评估输出用于写入代码的分支部分的正确结果的选择信号 结果寄存器。

公开(公告)号：US20110197050A1

公开(公告)日：2011-08-11

申请号：US12848876

申请日：2010-08-02

申请人： Claudio Genta ,  Alberto Manzone

发明人： Claudio Genta ,  Alberto Manzone

IPC分类号： G06F9/318

CPC分类号： G06F9/30079 ,  G06F9/30061 ,  G06F9/327

摘要： A microprogrammable electronic device comprises a code memory storing a plurality of instructions. At least one instruction, when executed by the device, causes the device to enter into a wait state associated with a plurality of predefined wait state exit conditions. The device is configured to load into an electronic table each condition together with a corresponding code memory address of an instruction to be executed when the condition occurs; to execute, when is in the wait state, a wait instruction stored in the code memory and which, when executed, is such as to cause the device to check simultaneously the conditions loaded into said electronic table to detect if condition occurs; and, if a condition occurs, to exit from said wait state and to execute the instruction stored in the code memory at the code memory address loaded into the electronic table together with the condition that occurred.

摘要翻译： 微程序化的电子设备包括存储多个指令的代码存储器。 当由设备执行时，至少一个指令使得设备进入与多个预定等待状态退出条件相关联的等待状态。 该装置被配置为在条件发生时将每个条件加载到要执行的指令的相应代码存储器地址的电子表中; 当处于等待状态时执行存储在代码存储器中的等待指令，并且当被执行时，使得设备同时检查加载到所述电子表中的条件以检测是否发生条件; 并且如果出现条件，则退出所述等待状态，并且与发生的条件一起执行与加载到电子表中的代码存储器地址存储在代码存储器中的指令。

公开(公告)号：US07953961B1

公开(公告)日：2011-05-31

申请号：US11880863

申请日：2007-07-23

申请人： Richard Win Thaik ,  John Gregory Favor ,  Joseph Byron Rowlands ,  Leonard Eric Shar

发明人： Richard Win Thaik ,  John Gregory Favor ,  Joseph Byron Rowlands ,  Leonard Eric Shar

IPC分类号： G06F9/40

CPC分类号： G06F9/30061 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3836

摘要： An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution circuit, receive an indication that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, and switch, based on the indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.

摘要翻译： 用于处理器的指令处理电路包括解码器电路，高速缓存电路，可操作以选择下一个操作序列的定序器电路，以及可操作以将下一个操作序列传送到执行电路的操作提取电路，接收指示 定序器电路的排序动作在执行电路之前排序，并且基于指示，在高速缓存电路和解码器电路之间切换操作提取电路的源。

公开(公告)号：US07721070B2

公开(公告)日：2010-05-18

申请号：US12235215

申请日：2008-09-22

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/30

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果存储在临时数据寄存器中，直到执行所有先前的指令为止，从而按顺序退出执行的指令。

公开(公告)号：US07711928B2

公开(公告)日：2010-05-04

申请号：US11082282

申请日：2005-03-16

申请人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

发明人： Marc Tremblay ,  Shailender Chaudhry ,  Quinn A. Jacobson

IPC分类号： G06F9/30

CPC分类号： G06F9/30061 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842

摘要： A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a first computer program instruction. Execution continues with execution of the second computer program instruction upon the status being a first status. Alternatively, a third computer program instruction is executed upon the status being a second status different from the first status. Thus, execution of the first computer program instruction allows control of the memory hierarchy, which in turn give the user control of the memory hierarchy.

摘要翻译： 为用户提供了通过软件对存储器层次结构进行抽样的方法。 这允许用户通过软件来增强内存级并行性。 响应于第一计算机程序指令的执行，读取执行第二计算机程序指令所需的信息的状态。 在状态为第一状态时，继续执行第二计算机程序指令。 或者，在状态是与第一状态不同的第二状态的情况下执行第三计算机程序指令。 因此，第一计算机程序指令的执行允许对存储器层次的控制，这进而使得用户对存储器层级进行控制。

公开(公告)号：US20090249047A1

公开(公告)日：2009-10-01

申请号：US12059957

申请日：2008-03-31

申请人： Daniel Citron

发明人： Daniel Citron

IPC分类号： G06F9/30

CPC分类号： G06F9/30061 ,  G06F9/324

摘要： A method and system for relative multiple-target branch instruction execution in a processor is provided. One implementation involves receiving an instruction for execution; determining a next instruction to execute based on multiple condition bits or outcomes of a comparison by the current instruction; obtaining a specified instruction offset in the current instruction; and using the offset as the basis for multiple instruction targets based on said outcomes, wherein the number of conditional branches is reduced.

摘要翻译： 提供了一种用于在处理器中执行相对多目标分支指令的方法和系统。 一个实现涉及接收执行指令; 基于当前指令的多个条件比特或比较结果确定下一个要执行的指令; 在当前指令中获取指定的指令偏移量; 并且基于所述结果使用偏移量作为多个指令目标的基础，其中条件分支的数量减少。

公开(公告)号：US07028171B2

公开(公告)日：2006-04-11

申请号：US10107266

申请日：2002-03-28

申请人： Gad Sheaffer

发明人： Gad Sheaffer

IPC分类号： G06F9/40

CPC分类号： G06F9/30094 ,  G06F9/30061 ,  G06F9/30181 ,  G06F9/3842

摘要： The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.

摘要翻译： 本发明涉及一种在处理器中提供N路选择指令的方法和系统。 具体地，提供N路选择指令的方法包括将指令解码为N路选择指令。 该方法还包括使用来自多个并行控制寄存器的信息从多个指令操作数中选择至少一对源操作数。 所述方法还包括从所选择的至少一对源操作数中的每一个选择最终源操作数，并输出所选择的最终源操作数中的每一个。 一般来说，任何N路选择指令都将具有M =对数2级的运行阶段。

公开(公告)号：US06986024B2

公开(公告)日：2006-01-10

申请号：US10283177

申请日：2002-10-30

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F13/18

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US06948052B2

公开(公告)日：2005-09-20

申请号：US10282207

申请日：2002-10-29

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F9/40 ,  G06F13/16

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US20040215675A1

公开(公告)日：2004-10-28

申请号：US10475945

申请日：2004-04-08

发明人： Takatoshi Nakamura ,  Akihiro Yokota

IPC分类号： G06F007/00

CPC分类号： G06F9/30061 ,  G06F9/30094

摘要： A calculation apparatus outputting a calculation result in accordance with an input condition and capable of increasing the processing speed. As a data of an address corresponding to an input condition of an calculation formula, its calculation result is stored in a memory and when the input condition is input to the memory, the calculation result is output. Moreover, the calculation apparatus executes calculation of a predetermined calculation formula and by learning, can output a calculation result at a high speed with a simple configuration. Storage means for outputting data corresponding to an address stores a calculation formula in which input is correlated to an address and output is correlated to data, and the calculation formula is selectively stored in accordance with the use frequency of the calculation formula.

摘要翻译： 计算装置，根据输入条件输出计算结果，并且能够提高处理速度。 作为与计算公式的输入条件对应的地址的数据，其计算结果存储在存储器中，并且当输入条件被输入到存储器时，输出计算结果。 此外，计算装置执行预定计算公式的计算，并且通过学习，可以以简单的配置高速输出计算结果。 用于输出与地址相对应的数据的存储装置存储与数据相关的输入与输出相关的计算公式，并且根据计算公式的使用频率选择性地存储计算公式。