公开(公告)号：US10303545B1

公开(公告)日：2019-05-28

申请号：US15827285

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. Meaney ,  Christian Jacobi ,  Barry M. Trager

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/15 ,  G11C29/52

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.

公开(公告)号：US20180367166A1

公开(公告)日：2018-12-20

申请号：US15830526

申请日：2017-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Glenn D. Gilda ,  Patrick J. Meaney ,  Arthur O'Neill ,  Barry M. Trager

IPC: H03M13/00 ,  H03M13/15

Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.