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公开(公告)号：US11960426B2
公开(公告)日：2024-04-16
申请号：US17804904
申请日：2022-06-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Rajat Rao , Patrick James Meaney , Glenn David Gilda , Michael Jason Cade , Robert J Sonnelitter, III , Hubert Harrer , Xiaomin Duan , Christian Jacobi , Arthur O'Neill
IPC: G06F13/36
CPC classification number: G06F13/36
Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.
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公开(公告)号：US11449397B2
公开(公告)日：2022-09-20
申请号：US16567308
申请日：2019-09-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Gregory J. Fredeman , Glenn David Gilda , Thomas E. Miller , Arthur O'Neill
Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.
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公开(公告)号：US20210073087A1
公开(公告)日：2021-03-11
申请号：US16567308
申请日：2019-09-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Gregory J. FREDEMAN , Glenn David Gilda , Thomas E. Miller , Arthur O'Neill
IPC: G06F11/20 , G06F12/0875 , G06F11/16 , G06F11/10 , G11C29/30
Abstract: A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.
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公开(公告)号：US20200327058A1
公开(公告)日：2020-10-15
申请号：US16380307
申请日：2019-04-10
Applicant: International Business Machines Corporation
Inventor： Ekaterina M. Ambroladze , Tim Bronson , Robert J. Sonnelitter, III , Deanna P. D. Berger , Chad G. Wilson , Kenneth Douglas Klapproth , Arthur O'Neill , Michael A. Blake , Guy G. Tracy
IPC: G06F12/0815
Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.
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公开(公告)号：US20200264977A1
公开(公告)日：2020-08-20
申请号：US16275436
申请日：2019-02-14
Applicant: International Business Machines Corporation
Inventor： Arun Iyengar , Tim Bronson , Michael Andrew Blake , Vesselina Papazova , Arthur O'Neill , Jason D. Kohl1 , Kenneth Klapproth
IPC: G06F12/0806 , G06F12/0817
Abstract: Provided are systems, methods, and media for simultaneous, non-atomic request processing of snooped operations of a broadcast scope within a SMP system. An example method includes detecting, by a first controller, based on a set of coherency resolution conditions, whether there are coherency resolution problems between two snooped operations. The method includes in response to detecting, by the first controller, that coherency resolution problems will not result, transmitting, from the first controller to a second controller, an indication signal indicating that coherency resolution problems will not result from the operation. The set of coherency resolution conditions includes: (a) detecting that a second operation of the two snooped operations operation is of a predetermined type, (b) detecting at time of snooping of the second operation that a directory state does not allow for exclusive data, and (c) detecting that the first controller has started committing to an update.
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Patent Agency Ranking
公开(公告)号：US20180367166A1
公开(公告)日：2018-12-20
申请号：US15830526
申请日：2017-12-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Glenn D. Gilda , Patrick J. Meaney , Arthur O'Neill , Barry M. Trager
Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
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公开(公告)号：US11461151B2
公开(公告)日：2022-10-04
申请号：US17237167
申请日：2021-04-22
Applicant: International Business Machines Corporation
Inventor： Robert J. Sonnelitter, III , Michael Fee , Craig R. Walters , Arthur O'Neill , Matthias Klein
IPC: G06F9/52 , G06F9/48 , G06F12/0802 , G06F9/54 , G06F9/38
Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.
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公开(公告)号：US20210240548A1
公开(公告)日：2021-08-05
申请号：US17237167
申请日：2021-04-22
Applicant: International Business Machines Corporation
Inventor： Robert J. Sonnelitter, III , Michael Fee , Craig R. Walters , Arthur O'Neill , Matthias Klein
IPC: G06F9/52 , G06F9/48 , G06F12/0802 , G06F9/54 , G06F9/38
Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.
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公开(公告)号：US10831661B2
公开(公告)日：2020-11-10
申请号：US16380307
申请日：2019-04-10
Applicant: International Business Machines Corporation
Inventor： Ekaterina M. Ambroladze , Tim Bronson , Robert J. Sonnelitter, III , Deanna P. D. Berger , Chad G. Wilson , Kenneth Douglas Klapproth , Arthur O'Neill , Michael A. Blake , Guy G. Tracy
IPC: G06F12/0815
Abstract: Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.
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公开(公告)号：US20230393999A1
公开(公告)日：2023-12-07
申请号：US17804904
申请日：2022-06-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Rajat Rao , Patrick James Meaney , Glenn David Gilda , Michael Jason Cade , Robert J Sonnelitter, III , Hubert Harrer , Xiaomin Duan , Christian Jacobi , Arthur O'Neill
CPC classification number: G06F15/8038 , G06F13/36
Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.
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