In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture

    公开(公告)号:US10340002B1

    公开(公告)日:2019-07-02

    申请号:US15941558

    申请日:2018-03-30

    Abstract: A resistive processing unit (RPU) device includes a weight storage device to store a weight voltage which corresponds to a weight value of the RPU device, and a read transistor having a gate connected to the weight storage device, and first and second source/drain terminals connected to first and second control ports, respectively. A current source connected to the second source/drain terminal generates a fixed reference current. The read transistor generates a weight current in response to the weight voltage. A read current output from the second control port represents a signed weight value of the RPU device. A magnitude of the read current is equal to a difference between the weight current and the fixed reference current. The sign of the read current is positive when the weight current is greater than the fixed reference current, and negative when the weight current is less than the fixed reference current.

    CONVOLUTIONAL NEURAL NETWORKS USING RESISTIVE PROCESSING UNIT ARRAY

    公开(公告)号:US20180075338A1

    公开(公告)日:2018-03-15

    申请号:US15480597

    申请日:2017-04-06

    Inventor: Tayfun Gokmen

    Abstract: Technical solutions are described for implementing a convolutional neural network (CNN) using resistive processing unit (RPU) array. An example method includes configuring an RPU array corresponding to a convolution layer in the CNN based on convolution kernels of the layer. The method further includes performing forward pass computations via the RPU array by transmitting voltage pulses corresponding to input data to the RPU array, and storing values corresponding to output currents from the RPU arrays as output maps. The method further includes performing backward pass computations via the RPU array by transmitting voltage pulses corresponding to error of the output maps, and storing the output currents from the RPU arrays as backward error maps. The method further includes performing update pass computations via the RPU array by transmitting voltage pulses corresponding to the input data of the convolution layer and the error of the output maps to the RPU array.

    COMPUTER ARCHITECTURE WITH RESISTIVE PROCESSING UNITS

    公开(公告)号:US20170124025A1

    公开(公告)日:2017-05-04

    申请号:US14928970

    申请日:2015-10-30

    Inventor: Tayfun Gokmen

    CPC classification number: G06F15/8007 G06F15/7867 G11C13/0007

    Abstract: A processor includes an array of resistive processing units connected between row and column lines with a resistive element. A first single instruction, multiple data processing unit (SIMD) is connected to the row lines. A second SIMD is connected to the column lines. A first instruction issuer is connected to the first SIMD to issue instructions to the first SIMD, and a second instruction issuer is connected to the second SIMD to issue instructions to the second SIMD such that the processor is programmable and configurable for specific operations depending on an issued instruction set.

    REAL TIME SIMULATION MONITORING
    15.
    发明申请
    REAL TIME SIMULATION MONITORING 审中-公开
    实时模拟监测

    公开(公告)号:US20160112274A1

    公开(公告)日:2016-04-21

    申请号:US14515563

    申请日:2014-10-16

    Abstract: A method for monitoring at least one simulation program includes capturing, by a computer, a plurality of simulation data from the at least one simulation program, the capturing is performed in real time while the at least one simulation program is continuously streaming the plurality of simulation data, analyzing, by the computer, the captured plurality of simulation data using a streaming data software, identifying a plurality of predefined criteria within the analyzed plurality of simulation data, the plurality of predefined criteria includes at least one of an event, a result and a variable, and providing feedback to the at least one simulation program to modify a plurality of simulation parameters according to the at least one identified event, result and variable.

    Abstract translation: 一种用于监视至少一个模拟程序的方法包括由计算机捕获来自所述至少一个仿真程序的多个模拟数据,所述捕获被实时执行,同时所述至少一个模拟程序持续地流式传输所述多个模拟 数据,由计算机分析所捕获的多个模拟数据,使用流式数据软件,识别所分析的多个模拟数据内的多个预定标准,所述多个预定标准包括事件,结果和 变量,并且根据所述至少一个识别的事件,结果和变量向所述至少一个模拟程序提供反馈以修改多个模拟参数。

    SOLAR CELL CHARACTERISTICS DETERMINATION
    16.
    发明申请
    SOLAR CELL CHARACTERISTICS DETERMINATION 有权
    太阳能电池特性测定

    公开(公告)号:US20140136129A1

    公开(公告)日:2014-05-15

    申请号:US13675928

    申请日:2012-11-13

    Abstract: An apparatus for determining solar cell characteristics includes a quantum efficiency measurement tool configured to measure an external quantum efficiency of the solar cell and a reflectivity measurement tool configured to measure the reflectivity of the solar cell. The apparatus also includes a capacitance measurement tool configured to measure the capacitance of the solar cell and a processor configured to calculate a diffusion length of the solar cell based on the measured quantum efficiency, reflectivity and capacitance of the solar cell.

    Abstract translation: 一种用于确定太阳能电池特性的装置包括:量子效率测量工具,被配置为测量太阳能电池的外部量子效率;以及反射率测量工具,被配置为测量太阳能电池的反射率。 该装置还包括:电容测量工具,被配置为测量太阳能电池的电容;以及处理器,被配置为基于所测量的量子效率,太阳能电池的反射率和电容来计算太阳能电池的扩散长度。

    DNN training with asymmetric RPU devices

    公开(公告)号:US11562249B2

    公开(公告)日:2023-01-24

    申请号:US16400674

    申请日:2019-05-01

    Inventor: Tayfun Gokmen

    Abstract: In a method of training a DNN, a weight matrix (W) is provided as a linear combination of matrices/arrays A and C. In a forward cycle, an input vector x is transmitted through arrays A and C and output vector y is read. In a backward cycle, an error signal δ is transmitted through arrays A and C and output vector z is read. Array A is updated by transmitting input vector x and error signal δ through array A. In a forward cycle, an input vector ei is transmitted through array A and output vector y′ is read. ƒ(y′) is calculated using y′. Array C is updated by transmitting input vector ei and ƒ(y′) through array C. A DNN is also provided.

    Acceleration of convolutional neural networks on analog arrays

    公开(公告)号:US11443176B2

    公开(公告)日:2022-09-13

    申请号:US16362031

    申请日:2019-03-22

    Abstract: Mechanisms are provided for acceleration of convolutional neural networks on analog arrays. Input ports receive image signals from frames in an input image. Input memory arrays store the image signals received from the input ports into a respective input memory location to create a plurality of image sub-regions in input memory arrays. A distributor associated each of a set of analog array tiles in an analog array to a part of image sub-regions of the input memory arrays, so that one or more of a set of analog memory components is associated with the image signals in a distribution order to create a respective output signal. An assembler stores each of the respective output signals into one of a set of memory outputs in an output order that is determined by the distribution order.

Patent Agency Ranking