公开(公告)号：US06784822B1

公开(公告)日：2004-08-31

申请号：US10693215

申请日：2003-10-24

申请人： Michael A. Nix ,  Ahmed Younis

发明人： Michael A. Nix ,  Ahmed Younis

IPC分类号： H03M138

CPC分类号： H03M1/16 ,  H03M1/60

摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

公开(公告)号：US06586964B1

公开(公告)日：2003-07-01

申请号：US10013438

申请日：2001-12-10

申请人： Michael Kent ,  Michael A. Nix

发明人： Michael Kent ,  Michael A. Nix

IPC分类号： B65H2318

CPC分类号： H04L25/0298

摘要： A system for calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system is provided. The system includes an adjustable termination resistor located on a chip and a reference termination resistor located off the chip. A bias circuit coupled to the adjustable termination resistor and the reference termination resistor causes the same current to flow through the adjustable termination resistor and the reference termination resistor. A comparator is configured to compare a first voltage drop across the adjustable termination resistor and a second voltage drop across the reference termination resistor. A control circuit is coupled to receive an output signal from the comparator. If the output signal indicates that the adjustable termination resistor has a desirable value with respect to the reference termination resistor, then the control circuit stops the calibration operation. Otherwise, the control circuit modifies the adjustable termination resistor and repeats the calibration cycle.

摘要翻译： 提供了一种用于校准用于低电压差分信号（LVDS）系统的可调终端电阻器的系统。 该系统包括位于芯片上的可调节终端电阻器和位于芯片外部的参考终端电阻器。 耦合到可调终端电阻器和参考终端电阻器的偏置电路使得相同的电流流过可调终端电阻器和参考终端电阻器。 比较器被配置为比较可调终端电阻器两端的第一电压降和参考端接电阻器两端的第二压降。 控制电路被耦合以从比较器接收输出信号。 如果输出信号指示可调终端电阻器相对于参考终端电阻器具有期望值，则控制电路停止校准操作。 否则，控制电路修改可调终端电阻并重复校准周期。

公开(公告)号：US5299144A

公开(公告)日：1994-03-29

申请号：US900000

申请日：1992-06-17

申请人： John G. Bartkowiak ,  Michael A. Nix

发明人： John G. Bartkowiak ,  Michael A. Nix

IPC分类号： G06F17/10 ,  G06F17/16 ,  G06F7/38 ,  G06F15/336

CPC分类号： G06F17/16

摘要： The present invention provides an apparatus and method for generating a covariance matrix. According to one aspect of the invention, an apparatus is provided which generally includes a memory, a circular buffer, a multiply-accumulator, and an arithmetic logic unit. The memory contains an array of values representative of a plurality of samples, and the circular buffer is configured to provide a predetermined number of memory locations. A method for generating the covariance matrix is further provided which uses the architecture listed above to efficiently generate a covariance matrix based on the values in the memory. In one aspect of the invention, the method provides that the memory, the circular buffer, the multiply-accumulator, and the arithmetic logic unit, all operate in parallel to fully exploit the resources provided by the architecture.

摘要翻译： 本发明提供了一种用于产生协方差矩阵的装置和方法。 根据本发明的一个方面，提供一种通常包括存储器，循环缓冲器，乘法累加器和算术逻辑单元的装置。 存储器包含表示多个样本的值的数组，并且循环缓冲器被配置为提供预定数量的存储器位置。 还提供了一种用于产生协方差矩阵的方法，其使用上面列出的架构来基于存储器中的值有效地生成协方差矩阵。 在本发明的一个方面中，该方法提供了存储器，循环缓冲器，乘法累加器和算术逻辑单元，它们都是并行操作的，以充分利用由架构提供的资源。

公开(公告)号：US5282153A

公开(公告)日：1994-01-25

申请号：US44891

申请日：1993-04-06

申请人： John G. Bartkowiak ,  Michael A. Nix

发明人： John G. Bartkowiak ,  Michael A. Nix

IPC分类号： G06F7/38 ,  G06F7/57 ,  G06F17/10

CPC分类号： G06F7/57 ,  G06F7/4991 ,  G06F7/49921

摘要： An arithmetic logic unit includes first and second buses for efficient operations upon multiple-bit operands. The arithmetic logic unit includes, in addition to the first and second buses, a shift register having an input coupled to the first bus and an output, a summer having a first input coupled to the shift register output, a second input coupled to the second bus, and an output, and an accumulator having an input coupled to the summer output and an output coupled to the first bus. The arithmetic logic unit further includes a buffer having an input also coupled to the summer output and an output coupled to the second bus. The summer provides two's compliment inversion when required and the shift register performs sign bit force zero, right shifting, and masking operations. In addition, an overflow detector and overflow correction detect and correct overflow conditions without requiring additional operating cycles.

摘要翻译： 算术逻辑单元包括用于在多位操作数上有效操作的第一和第二总线。 除了第一和第二总线之外，算术逻辑单元还包括具有耦合到第一总线和输出的输入的移位寄存器，具有耦合到移位寄存器输出的第一输入的加法器，耦合到第二总线的第二输入端 总线和输出，以及具有耦合到加法器输出的输入和耦合到第一总线的输出的累加器。 算术逻辑单元还包括具有耦合到加法器输出的输入的缓冲器和耦合到第二总线的输出。 当需要时，夏季提供两次的补码反转，移位寄存器执行符号位力零位，右移和掩蔽操作。 此外，溢出检测器和溢出校正检测并校正溢出条件，而不需要额外的工作循环。

公开(公告)号：US07978118B1

公开(公告)日：2011-07-12

申请号：US12697789

申请日：2010-02-01

申请人： Ahmed Abdell-Ra'oof Younis ,  Michael A. Nix

发明人： Ahmed Abdell-Ra'oof Younis ,  Michael A. Nix

IPC分类号： H03M1/34

CPC分类号： H03M1/0695 ,  H03M1/403

摘要： A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series. Each bit pair is mapped to a corresponding two-bit code value and the resulting code values are used to generate the digital value.

摘要翻译： 1.5位算法模数转换器（ADC）产生代表输入电压的数字值。 ADC实现了转换操作的一系列转换周期。 每个转换周期具有三个子周期：缩放子周期，第一采样子周期和第二采样子周期。 在缩放子周期中，来自先前转换周期的剩余电压加倍以产生第一电压。 在第一采样子周期中，基于第一电压的极性来确定相应位对的第一位。 基于第一电压的极性，第一电压被增加或减小参考电压以产生第二电压。 在第二采样子周期中，基于第二电压的极性来确定相应位对的第二位。 然后，基于第二电压的极性，第二电压被增加或减小参考电压，以产生用于该系列中的下一个转换周期的剩余电压。 每个位对被映射到相应的两位代码值，并且所得到的代码值用于生成数字值。

公开(公告)号：US07852161B2

公开(公告)日：2010-12-14

申请号：US12353619

申请日：2009-01-14

申请人： Michael A. Nix ,  Saeed Abbasi

发明人： Michael A. Nix ,  Saeed Abbasi

IPC分类号： H03B5/24

CPC分类号： H03K3/0315

摘要： An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

摘要翻译： 振荡器。 所述振荡器包括具有第一多个反相器的第一环形振荡器，第一多个电容器，每个具有耦合到所述第一多个反相器中对应的一个反相器的输出端的第一端子，第二环形振荡器，具有第二多个反相器 以及第二多个电容器，每个电容器具有耦合到第二多个逆变器中对应的一个的输出端子的第一端子。 第一多个电容器的第二端子耦合到第二多个逆变器中对应的一个的输出端子。 第二多个电容器的第二端子耦合到第一多个逆变器中对应的一个的输出端子。 振荡器被配置为提供差分时钟信号作为输出。

公开(公告)号：US20100176889A1

公开(公告)日：2010-07-15

申请号：US12353619

申请日：2009-01-14

申请人： Michael A. Nix ,  Saeed Abbasi

发明人： Michael A. Nix ,  Saeed Abbasi

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

摘要翻译： 振荡器。 所述振荡器包括具有第一多个反相器的第一环形振荡器，第一多个电容器，每个具有耦合到所述第一多个反相器中对应的一个反相器的输出端的第一端子，第二环形振荡器，具有第二多个反相器 以及第二多个电容器，每个电容器具有耦合到第二多个逆变器中对应的一个的输出端子的第一端子。 第一多个电容器的第二端子耦合到第二多个逆变器中对应的一个的输出端子。 第二多个电容器的第二端子耦合到第一多个逆变器中对应的一个的输出端子。 振荡器被配置为提供差分时钟信号作为输出。

公开(公告)号：US07084683B1

公开(公告)日：2006-08-01

申请号：US10837185

申请日：2004-04-30

申请人： Michael A. Nix

发明人： Michael A. Nix

IPC分类号： H03K3/283

CPC分类号： H03K3/356191 ,  H03K3/356113

摘要： A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first current-handling terminal connected to the first output terminal (Q), a second current-handling terminal connected to the second output terminal (Qb), and a first control terminal connected to a clock signal (C). A second transistor has a third current-handling terminal connected to the first output terminal (Q), a fourth current-handling terminal connected to the voltage supply terminal (Vss), and a second control terminal connected to a first input terminal (X1) of the output stage. A third transistor (440) has a fifth current-handling terminal connected to the first output terminal (Q), a sixth current-handling terminal connected to the voltage supply terminal (Vss), and a third control terminal connected to the second output terminal (Qb).

摘要翻译： 差分触发器（400）具有带有第一和第二输入端（X 1，X 2），第一和第二输出端（Q，Qb），第一电压供应端（Vss）， 第一晶体管（435）具有连接到第一输出端子（Q）的第一电流处理端子，连接到第二输出端子（Qb）的第二电流处理端子和连接到时钟信号（C ）。 第二晶体管具有连接到第一输出端子（Q）的第三电流处理端子，连接到电压端子（Vss）的第四电流处理端子和连接到第一输入端子（X 1）的第二控制端子 ）的输出级。 第三晶体管（440）具有连接到第一输出端子（Q）的第五电流处理端子，连接到电压源端子（Vss）的第六电流处理端子，以及连接到第二输出端子 （Qb）。

公开(公告)号：US06677879B1

公开(公告)日：2004-01-13

申请号：US10224976

申请日：2002-08-20

申请人： Michael A. Nix ,  Ahmed Younis

发明人： Michael A. Nix ,  Ahmed Younis

IPC分类号： H03M112

CPC分类号： H03M1/16 ,  H03M1/60

摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

摘要翻译： 输入模拟信号（105或405）的电压可以转换为频率取决于模拟输入信号（135或435）的信号。 分频器（115或415）可以被配置为将频率相关信号转换成分频信号（140或440）。 第一频率检测器（420a）或时间检测器（120a）可被配置为确定分频信号的频率，从而产生第一输出信号（145a或445a）。 第二频率检测器（420b）或时间检测器（120b）可以被配置为确定频率相关或非频率分频信号的频率，从而产生第二输出信号（145b或445b）。 第一和第二输出信号可以被后处理以产生代表输入模拟信号的数字输出信号（130或430）。

公开(公告)号：US5764581A

公开(公告)日：1998-06-09

申请号：US812931

申请日：1997-03-04

申请人： Michael A. Nix

发明人： Michael A. Nix

IPC分类号： G11C11/404 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/419 ,  H03F3/45

CPC分类号： G11C11/4099 ,  G11C11/404 ,  G11C11/4097

摘要： A dynamic RAM having two-transistor memory cells includes a top array of memory cells and a bottom array of memory cells, with a sense amplifier disposed between the two halves. The memory cells in each column of the top half are coupled to respective Bit.sub.-- Plus lines, and the memory cells in each column of the bottom half are coupled to respective Bit.sub.-- Minus lines. The Bit.sub.-- Plus lines and the Bit.sub.-- Minus lines are respectively coupled to Plus and Minus inputs of sense amplifiers for each column. One row of the top array includes only dummy cells, and one row of the bottom array includes only dummy cells. When a memory cell in the top array is read, a dummy cell in the lower array is activated, and when a memory cell in the bottom array is read, a dummy cell in the upper array is activated. That way, a two-transistor memory cell array can have a dual-differential bit line feature in order to reduce errors due to noise.

摘要翻译： 具有双晶体管存储单元的动态RAM包括存储单元的顶部阵列和存储单元的底部阵列，其中一个读出放大器设置在两个半部之间。 上半部分每列中的存储单元耦合到相应的Bit-Plus线，并且下半部分的每列中的存储器单元耦合到相应的Bit-Minus线。 Bit-Plus线和Bit-Minus线分别耦合到每列的读出放大器的Plus和Minus输入。 顶部阵列的一行仅包括虚拟单元，并且底部阵列的一行仅包括虚拟单元。 当读取顶部阵列中的存储单元时，下部阵列中的虚拟单元被激活，并且当读取底部阵列中的存储器单元时，上部阵列中的虚拟单元被激活。 这样，双晶体管存储单元阵列可以具有双差分位线特征，以便减少由噪声引起的误差。